Giacomo Travaglini 20ed09d1a1 arch-arm: LDTRSW was not marked as unpriviledged ...

Change-Id: If0f2b835e40ef011eba884b1dcd81f14531fd1ce
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24043
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

2020-02-10 09:41:11 +00:00

..

arch

arch-arm: LDTRSW was not marked as unpriviledged

2020-02-10 09:41:11 +00:00

base

arch,base,cpu: Add some default constructors/operators explicitly.

2020-02-01 09:25:30 +00:00

cpu

cpu: Make getIsaPtr return a BaseISA pointer.

2020-02-05 22:41:56 +00:00

dev

dev-arm: add boot_loader param to RealView setupBootLoader

2020-01-31 12:41:49 +00:00

doc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

base, gpu-compute: Move gpu AMOs into the generic header

2020-01-09 09:50:02 +00:00

kern

kern: When dumping dmesg, detect the byte order dynamically.

2019-10-30 22:29:23 +00:00

learning_gem5

mem-ruby: Allow Ruby to use all replacement policies in Classic

2019-10-11 03:29:29 +00:00

mem

mem: Make slicc generate some default methods explicitly.

2020-01-31 09:03:42 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

python: fix "fatal" usage in fdthelper

2019-12-18 09:15:14 +00:00

sim

arch,sim: Replace setuidFunc with ignoreFunc.

2020-02-08 13:05:45 +00:00

systemc

systemc: gem5_to_tlm: treat non-rw as ignorable command

2020-02-10 02:44:41 +00:00

unittest

tests: Added GTests for base/str.cc

2019-10-24 16:25:09 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Disable spurious "array-bounds" warnings for protobuf cc files.

2020-02-01 09:25:15 +00:00