Giacomo Travaglini 22273000d0 arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking ...

Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2019-09-06 20:00:34 +00:00

..

arch

arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking

2019-09-06 20:00:34 +00:00

base

stats: Create HDF5 stat files relative to simout

2019-09-02 12:20:12 +00:00

cpu

cpu: reset byte_enable across writeMem calls

2019-09-04 12:33:08 +00:00

dev

arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking

2019-09-06 20:00:34 +00:00

doc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

kern

kern: Replace an explicitly instantiated port proxy with one from the tc.

2019-05-30 14:20:03 +00:00

learning_gem5

mem: Move ruby protocols into a directory called ruby_protocol.

2019-08-23 21:13:07 +00:00

mem

ruby: Fix the way stall map size is checked for availability

2019-09-03 23:04:31 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

stats: Add support for listing available formats

2019-09-02 08:36:49 +00:00

sim

stats: Add support for hierarchical stats

2019-08-29 09:01:38 +00:00

systemc

mem, sim, systemc: Reorganize Port and co.s bind, unbind slightly.

2019-08-27 22:17:45 +00:00

unittest

python: Replace dict.has_key with 'key in dict'

2019-02-12 17:36:12 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Move the marshal binary to the build directory

2019-05-21 15:46:50 +00:00