4bdcb040d0
It makes much more sense for the Root Object to be create within the board and passed where required. Creating it in the Simulator class is not required. For this to work the signuature of the `_pre_instantiate` function in `AbstractBoard` has been updated to return the Root object.
120 lines
4.1 KiB
Python
120 lines
4.1 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This example runs a simple linux boot.
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Characteristics
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---------------
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* Runs exclusively on the RISC-V ISA with the classic caches
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* Assumes that the kernel is compiled into the bootloader
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* Automatically generates the DTB file
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"""
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import argparse
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import m5
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from m5.objects import Root
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from gem5.components.boards.experimental.lupv_board import LupvBoard
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from gem5.components.memory.single_channel import SingleChannelDDR3_1600
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.isas import ISA
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from gem5.resources.resource import obtain_resource
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from gem5.utils.requires import requires
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# Run a check to ensure the right version of gem5 is being used.
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requires(isa_required=ISA.RISCV)
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from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import (
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PrivateL1PrivateL2WalkCacheHierarchy,
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)
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parser = argparse.ArgumentParser(description="Runs Linux fs test with RISCV.")
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parser.add_argument(
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"cpu_type",
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choices=("timing", "atomic"),
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help="The type of CPU in the system",
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)
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parser.add_argument(
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"num_cpus", type=int, help="The number of CPU in the system"
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)
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parser.add_argument(
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"--max-ticks",
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type=int,
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required=False,
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default=m5.MaxTick,
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help="The maximum number of ticks to simulate. Used for testing.",
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)
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args = parser.parse_args()
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cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
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l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
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)
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# Setup the system memory.
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memory = SingleChannelDDR3_1600(size="128MiB")
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# Setup a single core Processor.
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if args.cpu_type == "atomic":
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processor = SimpleProcessor(
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cpu_type=CPUTypes.ATOMIC, num_cores=args.num_cpus, isa=ISA.RISCV
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)
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elif args.cpu_type == "timing":
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processor = SimpleProcessor(
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cpu_type=CPUTypes.TIMING, num_cores=args.num_cpus, isa=ISA.RISCV
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)
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# Setup the board.
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board = LupvBoard(
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clk_freq="1GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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# Set the Full System workload.
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board.set_kernel_disk_workload(
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kernel=obtain_resource(
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"riscv-lupio-linux-kernel", resource_version="1.0.0"
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),
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disk_image=obtain_resource(
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"riscv-lupio-busybox-img", resource_version="1.0.0"
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),
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)
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# Begin running of the simulation.
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print("Running with ISA: " + processor.get_isa().name)
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print()
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root = board._pre_instantiate()
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m5.instantiate()
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print("Beginning simulation!")
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exit_event = m5.simulate(args.max_ticks)
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print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}.")
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