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stdlib: Move Root obj creation from Simulator to Board

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It makes much more sense for the Root Object to be create within the
board and passed where required. Creating it in the Simulator class is
not required.

For this to work the signuature of the `_pre_instantiate` function in
`AbstractBoard` has been updated to return the Root object.
This commit is contained in:
Bobby R. Bruce
2024-08-22 05:16:47 -07:00
parent 4b3ba1daa6
commit 4bdcb040d0
10 changed files with 46 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
configs/example/lupv/run_lupv.py
View File

@@ -110,8 +110,7 @@ board.set_kernel_disk_workload(
# Begin running of the simulation.
print("Running with ISA: " + processor.get_isa().name)
print()
root = Root(full_system=True, system=board)
board._pre_instantiate()
root = board._pre_instantiate()
m5.instantiate()
print("Beginning simulation!")

25
src/python/gem5/components/boards/abstract_board.py
View File

@@ -41,6 +41,7 @@ from m5.objects import (
ClockDomain,
IOXBar,
Port,
Root,
SrcClockDomain,
System,
VoltageDomain,
@@ -391,13 +392,33 @@ class AbstractBoard:
self.get_cache_hierarchy()._post_instantiate()
self.get_memory()._post_instantiate()
def _pre_instantiate(self):
def _pre_instantiate(self, full_system: Optional[bool] = None) -> Root:
"""To be called immediately before ``m5.instantiate``. This is where
``_connect_things`` is executed by default."""
``_connect_things`` is executed by default and the root object is Root
object is created and returned.
:param full_system: Used to pass the full system flag to the board from
the Simulator module. **Note**: This was
implemented solely to maintain backawards
compatibility with while the Simululator module's
`full_system` flag is in state of deprecation. This
parameter will be removed when it is. When this
occurs whether a simulation is to be run in FS or
SE mode will be determined by the board set."""
# Connect the memory, processor, and cache hierarchy.
self._connect_things()
# Return the Root object.
return Root(
full_system=(
full_system
if full_system is not None
else self.is_fullsystem()
),
board=self,
)
def _connect_things_check(self):
"""
Here we check that connect things has been called and throw an

5
src/python/gem5/components/boards/arm_board.py
View File

@@ -28,6 +28,7 @@ import os
from abc import ABCMeta
from typing import (
List,
Optional,
Sequence,
Tuple,
)
@@ -327,8 +328,8 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
self.system_port = port
@overrides(AbstractBoard)
def _pre_instantiate(self):
super()._pre_instantiate()
def _pre_instantiate(self, full_system: Optional[bool] = None) -> None:
super()._pre_instantiate(full_system=full_system)
# Add the PCI devices.
self.pci_devices = self._pci_devices

9
src/python/gem5/components/boards/riscv_board.py
View File

@@ -26,7 +26,10 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
from typing import List
from typing import (
List,
Optional,
)
import m5
from m5.objects import (
@@ -498,7 +501,7 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
return "/dev/vda"
@overrides(AbstractSystemBoard)
def _pre_instantiate(self):
def _pre_instantiate(self, full_system: Optional[bool] = None):
if len(self._bootloader) > 0:
self.workload.bootloader_addr = 0x0
self.workload.bootloader_filename = self._bootloader[0]
@@ -507,7 +510,7 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
else:
self.workload.kernel_addr = 0x0
self.workload.entry_point = 0x80000000
self._connect_things()
super()._pre_instantiate(full_system=full_system)
@overrides(KernelDiskWorkload)
def _add_disk_to_board(self, disk_image: AbstractResource):

4
src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
View File

@@ -313,7 +313,7 @@ class RISCVMatchedBoard(
memory.set_memory_range(self.mem_ranges)
@overrides(AbstractSystemBoard)
def _pre_instantiate(self):
def _pre_instantiate(self, full_system: Optional[bool] = None) -> None:
if self._fs:
if len(self._bootloader) > 0:
self.workload.bootloader_addr = 0x0
@@ -326,7 +326,7 @@ class RISCVMatchedBoard(
self.workload.kernel_addr = 0x0
self.workload.entry_point = 0x80000000
self._connect_things()
super()._pre_instantiate(full_system=full_system)
def generate_device_tree(self, outdir: str) -> None:
"""Creates the ``dtb`` and ``dts`` files.

18
src/python/gem5/simulate/simulator.py
View File

@@ -664,22 +664,12 @@ class Simulator:
if not self._instantiated:
# Before anything else we run the AbstractBoard's
# `_pre_instantiate` function.
self._board._pre_instantiate()
root = Root(
full_system=(
self._full_system
if self._full_system is not None
else self._board.is_fullsystem()
),
board=self._board,
# `_pre_instantiate` function. This returns the root object which
# is required for instantiation.
self._root = self._board._pre_instantiate(
full_system=self._full_system
)
# We take a copy of the Root in case it's required elsewhere
# (for example, in `get_stats()`).
self._root = root
# The following is a bit of a hack. If a simulation is to use a KVM
# core then the `sim_quantum` value must be set. However, in the
# case of using a SwitchableProcessor the KVM cores may be

8
tests/gem5/kvm_fork_tests/configs/boot_kvm_fork_run.py
View File

@@ -207,15 +207,15 @@ print("Running with ISA: " + processor.get_isa().name)
print("Running with protocol: " + get_runtime_coherence_protocol().name)
print()
root = Root(full_system=True, system=motherboard)
# Disable the gdb ports. Required for forking.
m5.disableAllListeners()
root = motherboard._pre_instantiate()
# TODO: This of annoying. Is there a way to fix this to happen
# automatically when running KVM?
root.sim_quantum = int(1e9)
# Disable the gdb ports. Required for forking.
m5.disableAllListeners()
motherboard._pre_instantiate()
m5.instantiate()
# Simulate the inital boot with the starting KVM cpu

3
tests/gem5/replacement_policies/configs/run_replacement_policy.py
View File

@@ -83,9 +83,8 @@ motherboard = TestBoard(
memory=memory,
cache_hierarchy=cache_hierarchy,
)
root = Root(full_system=False, system=motherboard)
motherboard._pre_instantiate()
root = motherboard._pre_instantiate()
m5.instantiate()
generator.start_traffic()

3
tests/gem5/replacement_policies/run_replacement_policy.py
View File

@@ -83,9 +83,8 @@ motherboard = TestBoard(
memory=memory,
cache_hierarchy=cache_hierarchy,
)
root = Root(full_system=False, system=motherboard)
motherboard._pre_instantiate()
root = motherboard._pre_instantiate()
m5.instantiate()
generator.start_traffic()

4
tests/gem5/traffic_gen/configs/simple_traffic_run.py
View File

@@ -202,9 +202,7 @@ motherboard = TestBoard(
cache_hierarchy=cache_hierarchy,
)
root = Root(full_system=False, system=motherboard)
motherboard._pre_instantiate()
root = motherboard._pre_instantiate()
m5.instantiate()
generator.start_traffic()