e73655d038
This patch has been generated by applying flynt to the gem5 repo (ext has been excluded) JIRA: https://gem5.atlassian.net/browse/GEM5-831 Change-Id: I0935db6223d5426b99515959bde78e374cbadb04 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68957 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
82 lines
3.2 KiB
Python
82 lines
3.2 KiB
Python
# -*- coding: utf-8 -*-
|
|
# Copyright (c) 2015 Jason Power
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
""" This file creates a system with Ruby caches and runs the ruby random tester
|
|
See Part 3 in the Learning gem5 book:
|
|
http://gem5.org/documentation/learning_gem5/part3/MSIintro
|
|
|
|
IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
|
|
also needs to be updated. For now, email Jason <jason@lowepower.com>
|
|
|
|
"""
|
|
|
|
# import the m5 (gem5) library created when gem5 is built
|
|
import m5
|
|
|
|
# import all of the SimObjects
|
|
from m5.objects import *
|
|
|
|
from test_caches import TestCacheSystem
|
|
|
|
# create the system we are going to simulate
|
|
system = System()
|
|
|
|
# Set the clock frequency of the system (and all of its children)
|
|
system.clk_domain = SrcClockDomain()
|
|
system.clk_domain.clock = "1GHz"
|
|
system.clk_domain.voltage_domain = VoltageDomain()
|
|
|
|
# Set up the system
|
|
system.mem_mode = "timing" # Use timing accesses
|
|
system.mem_ranges = [AddrRange("512MB")] # Create an address range
|
|
|
|
# Create the tester
|
|
system.tester = RubyTester(
|
|
checks_to_complete=100, wakeup_frequency=10, num_cpus=2
|
|
)
|
|
|
|
# Create a simple memory controller and connect it to the membus
|
|
system.mem_ctrl = SimpleMemory(latency="50ns", bandwidth="0GB/s")
|
|
system.mem_ctrl.range = system.mem_ranges[0]
|
|
|
|
# Create the Ruby System
|
|
system.caches = TestCacheSystem()
|
|
system.caches.setup(system, system.tester, [system.mem_ctrl])
|
|
|
|
# set up the root SimObject and start the simulation
|
|
root = Root(full_system=False, system=system)
|
|
|
|
# Not much point in this being higher than the L1 latency
|
|
m5.ticks.setGlobalFrequency("1ns")
|
|
|
|
# instantiate all of the objects we've created above
|
|
m5.instantiate()
|
|
|
|
print("Beginning simulation!")
|
|
exit_event = m5.simulate()
|
|
print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")
|