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1ced08c85055d5da845ca549c0f5fcea65ee3e08
gem5/src/sim
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Brandon Potter 1ced08c850 syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc 
The class was crammed into syscall_emul.hh which has tons of forward
declarations and template definitions. To clean it up a bit, moved the
class into separate files and commented the class with doxygen style
comments. Also, provided some encapsulation by adding some accessors and
a mutator.

The syscallreturn.hh file was renamed syscall_return.hh to make it consistent
with other similarly named files in the src/sim directory.

The DPRINTF_SYSCALL macro was moved into its own header file with the
include the Base and Verbose flags as well.

--HG--
rename : src/sim/syscallreturn.hh => src/sim/syscall_return.hh
2016-11-09 14:27:40 -06:00
..
power
pwr: Closing power and thermal feedback loop
2016-06-06 17:16:44 +01:00
probe
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
arguments.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
arguments.hh
dev: Use shared_ptr for Arguments::Data
2014-10-16 05:49:45 -04:00
async.cc
base: Fix race in PollQueue and remove SIGALRM workaround
2013-11-29 14:36:10 +01:00
async.hh
base: Fix race in PollQueue and remove SIGALRM workaround
2013-11-29 14:36:10 +01:00
backtrace_glibc.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
backtrace_none.cc
sim: Add support for generating back traces on errors
2015-12-04 00:12:58 +00:00
backtrace.hh
sim: Add support for generating back traces on errors
2015-12-04 00:12:58 +00:00
byteswap.hh
base: Redesign internal frame buffer handling
2015-05-23 13:37:03 +01:00
clock_domain.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
clock_domain.hh
sim: Fix clock_domain unserialization
2016-04-01 16:22:44 +01:00
ClockDomain.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
clocked_object.cc
sim: Only print the power state transition warning once
2016-06-06 17:16:44 +01:00
clocked_object.hh
sim: Make clang happy
2016-06-07 14:27:49 +01:00
ClockedObject.py
sim: Adding support for power models
2016-06-06 17:16:44 +01:00
core.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
core.hh
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
cxx_config_ini.cc
config: Add the ability to read a config file using C++ and Python
2014-10-16 05:49:37 -04:00
cxx_config_ini.hh
config: Add the ability to read a config file using C++ and Python
2014-10-16 05:49:37 -04:00
cxx_config.cc
config: Add the ability to read a config file using C++ and Python
2014-10-16 05:49:37 -04:00
cxx_config.hh
config: Add the ability to read a config file using C++ and Python
2014-10-16 05:49:37 -04:00
cxx_manager.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
cxx_manager.hh
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
debug.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
debug.hh
sim: Add relative break scheduling
2015-10-09 14:27:09 -05:00
drain.cc
sim: Add additional debug information when draining
2015-12-11 17:29:53 +00:00
drain.hh
sim: Add support for notifying Drainable objects of a fork
2015-11-26 10:03:43 +00:00
dvfs_handler.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
dvfs_handler.hh
misc: Remove redundant compiler-specific defines
2015-10-12 04:07:59 -04:00
DVFSHandler.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
emul_driver.hh
sim, syscall_emul: Add mmap to EmulatedDriver
2016-09-13 23:12:46 -04:00
eventq_impl.hh
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
eventq.cc
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
eventq.hh
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
faults.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
faults.hh
arch: Use shared_ptr for all Faults
2014-10-16 05:49:51 -04:00
fd_entry.cc
base: refactor process class (specifically FdMap and friends)
2015-07-24 12:25:22 -07:00
fd_entry.hh
misc: Remove redundant compiler-specific defines
2015-10-12 04:07:59 -04:00
full_system.hh
clang: Fix recently introduced clang compilation errors
2012-03-19 06:35:04 -04:00
global_event.cc
sim: Fix resource leak in BaseGlobalEvent
2014-09-09 04:36:32 -04:00
global_event.hh
dev: Distributed Ethernet link for distributed gem5 simulations
2016-01-07 16:33:47 -06:00
init_signals.cc
sim: don't ignore SIG_TRAP
2016-01-17 18:27:46 -08:00
init_signals.hh
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
init.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
init.hh
scons: Track swig packages when loading embedded swig code
2016-06-28 03:50:00 -04:00
initparam_keys.hh
dev: Distributed Ethernet link for distributed gem5 simulations
2016-01-07 16:33:47 -06:00
insttracer.hh
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
InstTracer.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
linear_solver.cc
sim: Adding thermal model support
2015-05-12 10:26:47 +01:00
linear_solver.hh
sim: Adding thermal model support
2015-05-12 10:26:47 +01:00
main.cc
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
mathexpr.cc
sim: Make clang happy
2016-06-07 14:27:49 +01:00
mathexpr.hh
sim: Added library include to fix build errors on clang-703.0.31
2016-06-20 15:34:41 +01:00
microcode_rom.hh
CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
2008-10-12 15:59:21 -07:00
process_impl.hh
MEM: Make port proxies use references rather than pointers
2012-02-24 11:45:30 -05:00
process.cc
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
process.hh
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
Process.py
mem: Page Table map api modification
2014-11-23 18:01:09 -08:00
pseudo_inst.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
pseudo_inst.hh
dev: Add m5 op to toggle synchronization for dist-gem5.
2016-10-26 22:48:40 -04:00
py_interact.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
py_interact.hh
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
root.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
root.hh
misc: Add explicit overrides and fix other clang >= 3.5 issues
2015-10-12 04:08:01 -04:00
Root.py
sim: Remove redundant buildEnv import
2016-12-19 16:25:37 +00:00
SConscript
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
serialize.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
serialize.hh
sim: Add a checkpoint function to test for entries
2016-10-04 11:22:16 +01:00
sim_events.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
sim_events.hh
sim: Remove declaration of unused CountedDrainEvent
2017-01-03 17:31:39 +00:00
sim_exit.hh
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
sim_object.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
sim_object.hh
misc: Remove redundant compiler-specific defines
2015-10-12 04:07:59 -04:00
simulate.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
simulate.hh
sim: Update limit_event reuse to final version
2015-03-26 11:16:44 -04:00
stat_control.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
stat_control.hh
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
stat_register.cc
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
stat_register.hh
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
stats.hh
stats: make simTicks and simFreq accessible from stats.hh
2010-04-18 13:23:25 -07:00
sub_system.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
sub_system.hh
sim: Adding support for power models
2016-06-06 17:16:44 +01:00
SubSystem.py
sim: Adding thermal model support
2015-05-12 10:26:47 +01:00
syscall_debug_macros.hh
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
syscall_desc.cc
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
syscall_desc.hh
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
syscall_emul_buf.hh
syscall_emul: devirtualize BaseBufferArg methods
2014-10-22 15:53:34 -07:00
syscall_emul.cc
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
syscall_emul.hh
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
syscall_return.hh
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
system.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
system.hh
sim: Adding thermal model support
2015-05-12 10:26:47 +01:00
System.py
sim: Remove redundant export_method_cxx_predecls
2017-01-03 12:03:06 +00:00
ticked_object.cc
sim: Refactor the serialization base class
2015-07-07 09:51:03 +01:00
ticked_object.hh
misc: Add explicit overrides and fix other clang >= 3.5 issues
2015-10-12 04:08:01 -04:00
TickedObject.py
cpu: `Minor' in-order CPU model
2014-07-23 16:09:04 -05:00
voltage_domain.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
voltage_domain.hh
misc: Add explicit overrides and fix other clang >= 3.5 issues
2015-10-12 04:08:01 -04:00
VoltageDomain.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
vptr.hh
MEM: Make port proxies use references rather than pointers
2012-02-24 11:45:30 -05:00