Gabe Black 1a1ba692c3 sim: Move the MemPools object out of System and into SEWorkload. ...

This removes the need for all the FullSystem checks in the System class,
and simplifies that class in general.

Change-Id: Ie8a3bc67db9195027d2111009b15ca59221bdeb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50348
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-09-30 00:30:49 +00:00

..

arch

sim: Move the MemPools object out of System and into SEWorkload.

2021-09-30 00:30:49 +00:00

base

misc: Merge branch v21.1.0.2 hotfix branch into develop

2021-09-22 11:43:57 -07:00

cpu

cpu-o3: remove useless indirection from lsq to cpu

2021-09-29 07:32:27 +00:00

dev

arch-arm: Define an ArmRelease class to handle ISA extensions

2021-09-29 22:16:03 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

arch-vega: Add missing functions referenced by insts

2021-09-27 22:30:30 +00:00

kern

misc: Move MemPool based calls to the SEWorkload.

2021-09-21 02:05:32 +00:00

learning_gem5

misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].

2021-07-29 10:17:51 +00:00

mem

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

proto

python,scons: Move readCommand and compareVersions into site_scons.

2021-05-10 23:33:22 +00:00

python

python,scons: Break slicc's dependence on m5.util.

2021-09-24 21:23:41 +00:00

sim

sim: Move the MemPools object out of System and into SEWorkload.

2021-09-30 00:30:49 +00:00

systemc

systemc: Stop including mem/port.hh from the systemc headers.

2021-08-28 04:18:12 +00:00

Doxyfile

misc: Update the version to v21.1.0.2

2021-09-22 18:37:48 +00:00

SConscript

scons: Clone the gem5py_env environment in src/SConscript.

2021-09-29 23:55:35 +00:00