79bab1dc5d
Encapsulate every class inheriting from Abstract or Physical memories, and the memory controller in a memory namespace. Change-Id: I228f7e55efc395089e3616ae0a0a6325867bd782 Issued-on: https://gem5.atlassian.net/browse/GEM5-983 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47309 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com>
94 lines
4.4 KiB
Python
94 lines
4.4 KiB
Python
# Copyright (c) 2012-2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2013 Amin Farmahini-Farahani
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# Copyright (c) 2015 University of Kaiserslautern
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# Copyright (c) 2015 The University of Bologna
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.objects.QoSMemCtrl import *
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# Enum for memory scheduling algorithms, currently First-Come
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# First-Served and a First-Row Hit then First-Come First-Served
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class MemSched(Enum): vals = ['fcfs', 'frfcfs']
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# MemCtrl is a single-channel single-ported Memory controller model
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# that aims to model the most important system-level performance
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# effects of a memory controller, interfacing with media specific
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# interfaces
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class MemCtrl(QoSMemCtrl):
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type = 'MemCtrl'
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cxx_header = "mem/mem_ctrl.hh"
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cxx_class = 'gem5::memory::MemCtrl'
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# single-ported on the system interface side, instantiate with a
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# bus in front of the controller for multiple ports
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port = ResponsePort("This port responds to memory requests")
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# Interface to volatile, DRAM media
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dram = Param.DRAMInterface(NULL, "DRAM interface")
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# Interface to non-volatile media
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nvm = Param.NVMInterface(NULL, "NVM interface")
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# read and write buffer depths are set in the interface
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# the controller will read these values when instantiated
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# threshold in percent for when to forcefully trigger writes and
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# start emptying the write buffer
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write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
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# threshold in percentage for when to start writes if the read
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# queue is empty
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write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
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# minimum write bursts to schedule before switching back to reads
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min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
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"switching to reads")
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# scheduler, address map and page policy
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mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
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# pipeline latency of the controller and PHY, split into a
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# frontend part and a backend part, with reads and writes serviced
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# by the queues only seeing the frontend contribution, and reads
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# serviced by the memory seeing the sum of the two
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static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
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static_backend_latency = Param.Latency("10ns", "Static backend latency")
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command_window = Param.Latency("10ns", "Static backend latency")
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