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gem5/src
Giacomo Travaglini c3d356b43d arch-arm: Move generateTrap from MiscRegOp to ArmStaticInst (#1560)
System(Misc) register accesses are not the only trappable instructions.
We move the exception generation logic (generateTrap) from the
MiscRegOp64 to the base ArmStaticInst
2024-09-23 19:37:29 +02:00
..
2024-08-20 16:18:24 +01:00