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15ca4f2fc7c81bb3ade68cbff7d58bd01aa00d33
gem5/src/mem
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Lisa Hsu a5287efc58 slicc: Controllers attached to Sequencers no longer have to be named L1Cache.
2012-04-06 13:47:08 -07:00
..
cache
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
config
Fixes to get prefetching working again.
2009-02-16 08:56:40 -08:00
protocol
MOESI_hammer: tbe allocation and dependent wakeup fixes
2012-04-06 13:47:07 -07:00
ruby
sim-ruby: checkpointing fixes and dependent eventq improvements
2012-04-06 13:47:07 -07:00
slicc
slicc: Controllers attached to Sequencers no longer have to be named L1Cache.
2012-04-06 13:47:08 -07:00
abstract_mem.cc
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
abstract_mem.hh
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
AbstractMemory.py
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
bridge.cc
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
bridge.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
Bridge.py
MEM: Introduce the master/slave port roles in the Python classes
2012-02-13 06:43:09 -05:00
bus.cc
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
bus.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
Bus.py
MEM: Introduce the master/slave port roles in the Python classes
2012-02-13 06:43:09 -05:00
fs_translating_port_proxy.cc
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
fs_translating_port_proxy.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
mem_object.cc
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
mem_object.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
MemObject.py
Major changes to how SimObjects are created and initialized. Almost all
2007-07-23 21:51:38 -07:00
mport.cc
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
mport.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
packet_access.hh
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 08:34:21 -07:00
packet_queue.cc
MEM: Split SimpleTimingPort into PacketQueue and ports
2012-03-22 06:36:27 -04:00
packet_queue.hh
MEM: Split SimpleTimingPort into PacketQueue and ports
2012-03-22 06:36:27 -04:00
packet.cc
MemCmd: Add a command for invalidation requests to LSQ
2012-01-23 11:07:11 -06:00
packet.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
page_table.cc
Another merge with the main repository.
2012-01-07 02:16:37 -08:00
page_table.hh
SE/FS: Get rid of includes of config/full_system.hh.
2011-11-18 02:20:22 -08:00
physical.cc
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
physical.hh
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
port_proxy.cc
MEM: Make all the port proxy members const
2012-02-29 04:47:51 -05:00
port_proxy.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
port.cc
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
port.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
qport.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
request.hh
mem: fix cache stats to use request ids correctly
2012-02-12 16:07:39 -06:00
SConscript
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
se_translating_port_proxy.cc
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
se_translating_port_proxy.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
simple_mem.cc
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
simple_mem.hh
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
SimpleMemory.py
MEM: Enable multiple distributed generalized memories
2012-04-06 13:46:31 -04:00
tport.cc
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00
tport.hh
MEM: Introduce the master/slave port sub-classes in C++
2012-03-30 09:40:11 -04:00