Tom Rollet 133399c91d cpu-o3: remove useless indirection from lsq to cpu ...

Change-Id: Idd2d4277b542da728f0740590ae7ef9ae9b76629
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50731
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>

2021-09-29 07:32:27 +00:00

..

arch

arch-arm: Prefer haveEL over haveSecurity and haveVirtualization

2021-09-29 07:27:59 +00:00

base

misc: Merge branch v21.1.0.2 hotfix branch into develop

2021-09-22 11:43:57 -07:00

cpu

cpu-o3: remove useless indirection from lsq to cpu

2021-09-29 07:32:27 +00:00

dev

arch-arm: Syncronize GIC CPU interface when changing EL

2021-09-20 09:03:19 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

arch-vega: Add missing functions referenced by insts

2021-09-27 22:30:30 +00:00

kern

misc: Move MemPool based calls to the SEWorkload.

2021-09-21 02:05:32 +00:00

learning_gem5

misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].

2021-07-29 10:17:51 +00:00

mem

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

proto

python,scons: Move readCommand and compareVersions into site_scons.

2021-05-10 23:33:22 +00:00

python

python,scons: Break slicc's dependence on m5.util.

2021-09-24 21:23:41 +00:00

sim

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

systemc

systemc: Stop including mem/port.hh from the systemc headers.

2021-08-28 04:18:12 +00:00

Doxyfile

misc: Update the version to v21.1.0.2

2021-09-22 18:37:48 +00:00

SConscript

scons: Pull the rest of the embedPyFile function into marshal.py.

2021-09-24 21:24:06 +00:00