22c04190c6
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions.
335 lines
10 KiB
C++
335 lines
10 KiB
C++
/*
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* Copyright (c) 2013, 2015 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Giacomo Gabrielli
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* Andreas Sandberg
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*/
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#ifndef __DEV_ARM_GENERIC_TIMER_HH__
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#define __DEV_ARM_GENERIC_TIMER_HH__
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#include "arch/arm/isa_device.hh"
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#include "base/bitunion.hh"
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#include "dev/arm/base_gic.hh"
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#include "sim/core.hh"
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#include "sim/sim_object.hh"
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/// @file
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/// This module implements the global system counter and the local per-CPU
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/// architected timers as specified by the ARM Generic Timer extension (ARM
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/// ARM, Issue C, Chapter 17).
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class Checkpoint;
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class GenericTimerParams;
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class GenericTimerMemParams;
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/// Global system counter. It is shared by the architected timers.
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/// @todo: implement memory-mapped controls
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class SystemCounter : public Serializable
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{
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protected:
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/// Counter frequency (as specified by CNTFRQ).
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uint64_t _freq;
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/// Cached copy of the counter period (inverse of the frequency).
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Tick _period;
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/// Tick when the counter was reset.
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Tick _resetTick;
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uint32_t _regCntkctl;
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public:
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SystemCounter();
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/// Returns the current value of the physical counter.
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uint64_t value() const
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{
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if (_freq == 0)
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return 0; // Counter is still off.
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return (curTick() - _resetTick) / _period;
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}
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/// Returns the counter frequency.
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uint64_t freq() const { return _freq; }
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/// Sets the counter frequency.
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/// @param freq frequency in Hz.
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void setFreq(uint32_t freq);
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/// Returns the counter period.
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Tick period() const { return _period; }
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void setKernelControl(uint32_t val) { _regCntkctl = val; }
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uint32_t getKernelControl() { return _regCntkctl; }
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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private:
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// Disable copying
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SystemCounter(const SystemCounter &c);
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};
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/// Per-CPU architected timer.
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class ArchTimer : public Serializable
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{
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public:
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class Interrupt
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{
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public:
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Interrupt(BaseGic &gic, unsigned irq)
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: _gic(gic), _ppi(false), _irq(irq), _cpu(0) {}
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Interrupt(BaseGic &gic, unsigned irq, unsigned cpu)
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: _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {}
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void send();
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void clear();
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private:
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BaseGic &_gic;
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const bool _ppi;
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const unsigned _irq;
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const unsigned _cpu;
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};
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protected:
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/// Control register.
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BitUnion32(ArchTimerCtrl)
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Bitfield<0> enable;
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Bitfield<1> imask;
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Bitfield<2> istatus;
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EndBitUnion(ArchTimerCtrl)
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/// Name of this timer.
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const std::string _name;
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/// Pointer to parent class.
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SimObject &_parent;
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SystemCounter &_systemCounter;
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Interrupt _interrupt;
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/// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
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ArchTimerCtrl _control;
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/// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
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uint64_t _counterLimit;
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/// Offset relative to the physical timer (CNTVOFF)
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uint64_t _offset;
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/**
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* Timer settings or the offset has changed, re-evaluate
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* trigger condition and raise interrupt if necessary.
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*/
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void updateCounter();
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/// Called when the upcounter reaches the programmed value.
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void counterLimitReached();
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EventWrapper<ArchTimer, &ArchTimer::counterLimitReached>
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_counterLimitReachedEvent;
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public:
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ArchTimer(const std::string &name,
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SimObject &parent,
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SystemCounter &sysctr,
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const Interrupt &interrupt);
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/// Returns the timer name.
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std::string name() const { return _name; }
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/// Returns the CompareValue view of the timer.
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uint64_t compareValue() const { return _counterLimit; }
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/// Sets the CompareValue view of the timer.
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void setCompareValue(uint64_t val);
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/// Returns the TimerValue view of the timer.
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uint32_t timerValue() const { return _counterLimit - value(); }
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/// Sets the TimerValue view of the timer.
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void setTimerValue(uint32_t val);
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/// Sets the control register.
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uint32_t control() const { return _control; }
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void setControl(uint32_t val);
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uint64_t offset() const { return _offset; }
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void setOffset(uint64_t val);
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/// Returns the value of the counter which this timer relies on.
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uint64_t value() const;
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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private:
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// Disable copying
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ArchTimer(const ArchTimer &t);
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};
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class GenericTimer : public SimObject
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{
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public:
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GenericTimer(GenericTimerParams *p);
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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public:
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void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
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ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
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protected:
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struct CoreTimers {
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CoreTimers(GenericTimer &parent, unsigned cpu,
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unsigned _irqPhys, unsigned _irqVirt)
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: irqPhys(*parent.gic, _irqPhys, cpu),
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irqVirt(*parent.gic, _irqVirt, cpu),
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// This should really be phys_timerN, but we are stuck with
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// arch_timer for backwards compatibility.
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phys(csprintf("%s.arch_timer%d", parent.name(), cpu),
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parent, parent.systemCounter,
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irqPhys),
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virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
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parent, parent.systemCounter,
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irqVirt)
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{}
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ArchTimer::Interrupt irqPhys;
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ArchTimer::Interrupt irqVirt;
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ArchTimer phys;
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ArchTimer virt;
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private:
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// Disable copying
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CoreTimers(const CoreTimers &c);
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};
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CoreTimers &getTimers(int cpu_id);
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void createTimers(unsigned cpus);
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/// System counter.
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SystemCounter systemCounter;
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/// Per-CPU physical architected timers.
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std::vector<std::unique_ptr<CoreTimers>> timers;
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protected: // Configuration
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/// Pointer to the GIC, needed to trigger timer interrupts.
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BaseGic *const gic;
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/// Physical timer interrupt
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const unsigned irqPhys;
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/// Virtual timer interrupt
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const unsigned irqVirt;
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};
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class GenericTimerISA : public ArmISA::BaseISADevice
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{
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public:
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GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
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: parent(_parent), cpu(_cpu) {}
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void setMiscReg(int misc_reg, ArmISA::MiscReg val) override {
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parent.setMiscReg(misc_reg, cpu, val);
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}
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ArmISA::MiscReg readMiscReg(int misc_reg) override {
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return parent.readMiscReg(misc_reg, cpu);
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}
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protected:
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GenericTimer &parent;
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unsigned cpu;
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};
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class GenericTimerMem : public PioDevice
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{
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public:
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GenericTimerMem(GenericTimerMemParams *p);
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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public: // PioDevice
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AddrRangeList getAddrRanges() const override { return addrRanges; }
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Tick read(PacketPtr pkt) override;
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Tick write(PacketPtr pkt) override;
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protected:
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uint64_t ctrlRead(Addr addr, size_t size) const;
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void ctrlWrite(Addr addr, size_t size, uint64_t value);
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uint64_t timerRead(Addr addr, size_t size) const;
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void timerWrite(Addr addr, size_t size, uint64_t value);
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protected: // Registers
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static const Addr CTRL_CNTFRQ = 0x000;
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static const Addr CTRL_CNTNSAR = 0x004;
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static const Addr CTRL_CNTTIDR = 0x008;
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static const Addr CTRL_CNTACR_BASE = 0x040;
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static const Addr CTRL_CNTVOFF_LO_BASE = 0x080;
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static const Addr CTRL_CNTVOFF_HI_BASE = 0x084;
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static const Addr TIMER_CNTPCT_LO = 0x000;
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static const Addr TIMER_CNTPCT_HI = 0x004;
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static const Addr TIMER_CNTVCT_LO = 0x008;
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static const Addr TIMER_CNTVCT_HI = 0x00C;
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static const Addr TIMER_CNTFRQ = 0x010;
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static const Addr TIMER_CNTEL0ACR = 0x014;
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static const Addr TIMER_CNTVOFF_LO = 0x018;
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static const Addr TIMER_CNTVOFF_HI = 0x01C;
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static const Addr TIMER_CNTP_CVAL_LO = 0x020;
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static const Addr TIMER_CNTP_CVAL_HI = 0x024;
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static const Addr TIMER_CNTP_TVAL = 0x028;
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static const Addr TIMER_CNTP_CTL = 0x02C;
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static const Addr TIMER_CNTV_CVAL_LO = 0x030;
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static const Addr TIMER_CNTV_CVAL_HI = 0x034;
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static const Addr TIMER_CNTV_TVAL = 0x038;
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static const Addr TIMER_CNTV_CTL = 0x03C;
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protected: // Params
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const AddrRange ctrlRange;
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const AddrRange timerRange;
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const AddrRangeList addrRanges;
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protected:
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/// System counter.
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SystemCounter systemCounter;
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ArchTimer physTimer;
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ArchTimer virtTimer;
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};
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#endif // __DEV_ARM_GENERIC_TIMER_HH__
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