0df5635bdf
This patch is adding the NS bit to CHI requests to make sure they are properly tagged according to their security Change-Id: I33d3610edefbb5a05a6090e9125c35d4fb8bca58 Reviewed-by: Tiago Muck <tiago.muck@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
254 lines
8.8 KiB
C++
254 lines
8.8 KiB
C++
/*
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* Copyright (c) 2020-2021, 2024 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYREQUEST_HH__
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#define __MEM_RUBY_SLICC_INTERFACE_RUBYREQUEST_HH__
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#include <ostream>
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#include <vector>
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/ruby/common/WriteMask.hh"
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#include "mem/ruby/protocol/Message.hh"
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#include "mem/ruby/protocol/PrefetchBit.hh"
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#include "mem/ruby/protocol/RubyAccessMode.hh"
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#include "mem/ruby/protocol/RubyRequestType.hh"
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namespace gem5
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{
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namespace ruby
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{
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class RubyRequest : public Message
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{
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public:
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Addr m_PhysicalAddress;
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Addr m_LineAddress;
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RubyRequestType m_Type;
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Addr m_ProgramCounter;
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RubyAccessMode m_AccessMode;
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int m_Size;
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PrefetchBit m_Prefetch;
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PacketPtr m_pkt;
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ContextID m_contextId;
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WriteMask m_writeMask;
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DataBlock m_WTData;
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int m_wfid;
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uint64_t m_instSeqNum;
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bool m_htmFromTransaction;
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uint64_t m_htmTransactionUid;
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bool m_isTlbi;
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// Should be uint64, but SLICC complains about casts
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Addr m_tlbiTransactionUid;
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// GPU cache bypass flags. GLC bypasses L1 while SLC bypasses both L1 and
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// L2 if set to true. They are set to false by default and they must be
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// explicitly set to true in the program in order to bypass caches
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bool m_isGLCSet;
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bool m_isSLCSet;
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bool m_isSecure;
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RubyRequest(Tick curTime, uint64_t _paddr, int _len,
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uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode,
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PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No,
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ContextID _proc_id = 100, ContextID _core_id = 99)
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: Message(curTime),
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m_PhysicalAddress(_paddr),
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m_Type(_type),
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m_ProgramCounter(_pc),
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m_AccessMode(_access_mode),
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m_Size(_len),
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m_Prefetch(_pb),
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m_pkt(_pkt),
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m_contextId(_core_id),
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m_htmFromTransaction(false),
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m_htmTransactionUid(0),
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m_isTlbi(false),
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m_tlbiTransactionUid(0),
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m_isSecure(m_pkt->req->isSecure())
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{
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m_LineAddress = makeLineAddress(m_PhysicalAddress);
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if (_pkt) {
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m_isGLCSet = m_pkt->req->isGLCSet();
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m_isSLCSet = m_pkt->req->isSLCSet();
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} else {
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m_isGLCSet = 0;
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m_isSLCSet = 0;
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}
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}
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/** RubyRequest for memory management commands */
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RubyRequest(Tick curTime,
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uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode,
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PacketPtr _pkt, ContextID _proc_id, ContextID _core_id)
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: Message(curTime),
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m_PhysicalAddress(0),
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m_Type(_type),
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m_ProgramCounter(_pc),
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m_AccessMode(_access_mode),
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m_Size(0),
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m_Prefetch(PrefetchBit_No),
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m_pkt(_pkt),
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m_contextId(_core_id),
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m_htmFromTransaction(false),
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m_htmTransactionUid(0),
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m_isTlbi(false),
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m_tlbiTransactionUid(0),
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m_isSecure(m_pkt->req->isSecure())
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{
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assert(m_pkt->req->isMemMgmt());
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if (_pkt) {
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m_isGLCSet = m_pkt->req->isGLCSet();
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m_isSLCSet = m_pkt->req->isSLCSet();
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} else {
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m_isGLCSet = 0;
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m_isSLCSet = 0;
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}
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}
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RubyRequest(Tick curTime, uint64_t _paddr, int _len,
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uint64_t _pc, RubyRequestType _type,
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RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb,
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unsigned _proc_id, unsigned _core_id,
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int _wm_size, std::vector<bool> & _wm_mask,
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DataBlock & _Data,
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uint64_t _instSeqNum = 0)
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: Message(curTime),
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m_PhysicalAddress(_paddr),
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m_Type(_type),
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m_ProgramCounter(_pc),
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m_AccessMode(_access_mode),
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m_Size(_len),
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m_Prefetch(_pb),
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m_pkt(_pkt),
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m_contextId(_core_id),
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m_writeMask(_wm_size,_wm_mask),
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m_WTData(_Data),
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m_wfid(_proc_id),
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m_instSeqNum(_instSeqNum),
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m_htmFromTransaction(false),
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m_htmTransactionUid(0),
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m_isTlbi(false),
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m_tlbiTransactionUid(0),
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m_isSecure(m_pkt->req->isSecure())
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{
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m_LineAddress = makeLineAddress(m_PhysicalAddress);
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if (_pkt) {
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m_isGLCSet = m_pkt->req->isGLCSet();
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m_isSLCSet = m_pkt->req->isSLCSet();
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} else {
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m_isGLCSet = 0;
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m_isSLCSet = 0;
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}
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}
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RubyRequest(Tick curTime, uint64_t _paddr, int _len,
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uint64_t _pc, RubyRequestType _type,
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RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb,
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unsigned _proc_id, unsigned _core_id,
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int _wm_size, std::vector<bool> & _wm_mask,
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DataBlock & _Data,
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std::vector< std::pair<int,AtomicOpFunctor*> > _atomicOps,
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uint64_t _instSeqNum = 0)
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: Message(curTime),
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m_PhysicalAddress(_paddr),
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m_Type(_type),
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m_ProgramCounter(_pc),
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m_AccessMode(_access_mode),
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m_Size(_len),
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m_Prefetch(_pb),
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m_pkt(_pkt),
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m_contextId(_core_id),
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m_writeMask(_wm_size,_wm_mask,_atomicOps),
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m_WTData(_Data),
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m_wfid(_proc_id),
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m_instSeqNum(_instSeqNum),
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m_htmFromTransaction(false),
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m_htmTransactionUid(0),
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m_isTlbi(false),
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m_tlbiTransactionUid(0),
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m_isSecure(m_pkt->req->isSecure())
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{
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m_LineAddress = makeLineAddress(m_PhysicalAddress);
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if (_pkt) {
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m_isGLCSet = m_pkt->req->isGLCSet();
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m_isSLCSet = m_pkt->req->isSLCSet();
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} else {
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m_isGLCSet = 0;
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m_isSLCSet = 0;
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}
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}
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RubyRequest(Tick curTime) : Message(curTime) {}
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MsgPtr clone() const
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{ return std::shared_ptr<Message>(new RubyRequest(*this)); }
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Addr getLineAddress() const { return m_LineAddress; }
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Addr getPhysicalAddress() const { return m_PhysicalAddress; }
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const RubyRequestType& getType() const { return m_Type; }
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Addr getProgramCounter() const { return m_ProgramCounter; }
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const RubyAccessMode& getAccessMode() const { return m_AccessMode; }
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const int& getSize() const { return m_Size; }
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const PrefetchBit& getPrefetch() const { return m_Prefetch; }
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RequestPtr getRequestPtr() const { return m_pkt->req; }
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void setWriteMask(uint32_t offset, uint32_t len,
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std::vector< std::pair<int,AtomicOpFunctor*>> atomicOps);
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void print(std::ostream& out) const;
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bool functionalRead(Packet *pkt);
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bool functionalRead(Packet *pkt, WriteMask &mask);
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bool functionalWrite(Packet *pkt);
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};
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inline std::ostream&
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operator<<(std::ostream& out, const RubyRequest& obj)
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{
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obj.print(out);
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out << std::flush;
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return out;
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}
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} // namespace ruby
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} // namespace gem5
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#endif //__MEM_RUBY_SLICC_INTERFACE_RUBYREQUEST_HH__
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