Alec Roelke 096cdd508d arch-riscv: Fix floating-poing op classes ...

This patch applies correct miscellaneous or multiply-accumulate op
classes to floating point instructions which had previously been
incorrectly classed as add or multiply instructions.

Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb
Reviewed-on: https://gem5-review.googlesource.com/6521
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

2018-01-16 16:24:40 +00:00

..

alpha

arch: Fix a fatal_if in most of the arch's process classes.

2018-01-15 06:13:55 +00:00

arm

arch: Fix a fatal_if in most of the arch's process classes.

2018-01-15 06:13:55 +00:00

generic

arch,cpu: "virtualize" the TLB interface.

2017-12-22 23:16:03 +00:00

hsail

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

mips

arch: Fix a fatal_if in most of the arch's process classes.

2018-01-15 06:13:55 +00:00

null

scons: Stop generating inc.d in the isa parser.

2017-10-17 18:57:50 +00:00

power

arch: Fix a fatal_if in most of the arch's process classes.

2018-01-15 06:13:55 +00:00

riscv

arch-riscv: Fix floating-poing op classes

2018-01-16 16:24:40 +00:00

sparc

arch: Fix a fatal_if in most of the arch's process classes.

2018-01-15 06:13:55 +00:00

x86

arch,mem: Remove the default value for page size.

2018-01-11 06:30:15 +00:00

isa_parser.py

alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.

2017-11-02 09:43:35 +00:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

scons: Move Transform and termcap functionality into their own files.

2017-11-10 13:17:29 +00:00