Files
gem5/tests
Roger Chang 083566d0c8 arch-riscv: add RV32 ADFIMU_Zfh instruction tests
1. Add rv32 binary files into asmtests
2. Support Riscv CPU with 32 bits register to  simple_binary_run.py

Change-Id: I5cc4c2eeb7654a4acc2d167eb76d8b6522e65dd9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65533
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-12-30 22:56:01 +00:00
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