afee6296b5
The upgraders in util/cpt_upgraders have been able to check the root.isa element of checkpoints to determine what "the" ISA is for a simulation, as a quick way to bail out of that particular updater applies only to specific ISAs. We are moving away from the idea that there is a single ISA, and so this mechanism will no longer work. Fortunately, these cpt_upgraders are only relevant for old checkpoints. If a checkpoint doesn't have a root.isa element inside it at all, we know (as of this writing) that it is newer than all of these upgraders and hence they do not apply. Any new upgraders will have to be written to not rely on the root.isa field which will be removed. If that sort of field is still needed, it can be added somewhere else in the hierarchy, perhaps at the system level, or as part of the actual ISA object. The simplest way to implement this new behavior is to add a fallback option when an upgrader looks for root.isa, specifically ''. If the root.isa element does not exist, the script will get '' back, and this will not match whatever ISA it's trying to check against. The one even remotely more complicated script is isa-is-simobject.py which has several behaviors for different ISAs. In that case, we just explicitly check for '' and return early if that's what we found. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056 Change-Id: Ie78deccb2bac51f38224e62a28dd733cefd63ed7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48883 Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
67 lines
2.5 KiB
Python
67 lines
2.5 KiB
Python
# The ISA is now a separate SimObject, which means that we serialize
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# it in a separate section instead of as a part of the ThreadContext.
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def upgrader(cpt):
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isa = cpt.get('root', 'isa', fallback='')
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if isa == '':
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return
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isa_fields = {
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"arm" : ( "miscRegs" ),
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"sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr",
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"stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt",
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"tba", "pstate", "tl", "pil", "cwp", "gl", "hpstate",
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"htstate", "hintp", "htba", "hstick_cmpr",
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"strandStatusReg", "fsr", "priContext", "secContext",
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"partId", "lsuCtrlReg", "scratchPad",
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"cpu_mondo_head", "cpu_mondo_tail",
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"dev_mondo_head", "dev_mondo_tail",
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"res_error_head", "res_error_tail",
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"nres_error_head", "nres_error_tail",
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"tick_intr_sched",
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"cpu", "tc_num", "tick_cmp", "stick_cmp", "hstick_cmp"),
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"x86" : ( "regVal" ),
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}
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isa_fields = isa_fields.get(isa, [])
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isa_sections = []
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for sec in cpt.sections():
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import re
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re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec)
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# Search for all the execution contexts
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if not re_cpu_match:
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continue
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if re_cpu_match.group(2) != "0":
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# This shouldn't happen as we didn't support checkpointing
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# of in-order and O3 CPUs.
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raise ValueError("Don't know how to migrate multi-threaded CPUs "
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"from version 1")
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isa_section = []
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for fspec in isa_fields:
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for (key, value) in cpt.items(sec, raw=True):
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if key in isa_fields:
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isa_section.append((key, value))
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name = "%s.isa" % re_cpu_match.group(1)
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isa_sections.append((name, isa_section))
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for (key, value) in isa_section:
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cpt.remove_option(sec, key)
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for (sec, options) in isa_sections:
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# Some intermediate versions of gem5 have empty ISA sections
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# (after we made the ISA a SimObject, but before we started to
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# serialize into a separate ISA section).
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if not cpt.has_section(sec):
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cpt.add_section(sec)
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else:
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if cpt.items(sec):
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raise ValueError("Unexpected populated ISA section in old "
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"checkpoint")
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for (key, value) in options:
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cpt.set(sec, key, value)
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legacy_version = 4
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