afee6296b5
The upgraders in util/cpt_upgraders have been able to check the root.isa element of checkpoints to determine what "the" ISA is for a simulation, as a quick way to bail out of that particular updater applies only to specific ISAs. We are moving away from the idea that there is a single ISA, and so this mechanism will no longer work. Fortunately, these cpt_upgraders are only relevant for old checkpoints. If a checkpoint doesn't have a root.isa element inside it at all, we know (as of this writing) that it is newer than all of these upgraders and hence they do not apply. Any new upgraders will have to be written to not rely on the root.isa field which will be removed. If that sort of field is still needed, it can be added somewhere else in the hierarchy, perhaps at the system level, or as part of the actual ISA object. The simplest way to implement this new behavior is to add a fallback option when an upgrader looks for root.isa, specifically ''. If the root.isa element does not exist, the script will get '' back, and this will not match whatever ISA it's trying to check against. The one even remotely more complicated script is isa-is-simobject.py which has several behaviors for different ISAs. In that case, we just explicitly check for '' and return early if that's what we found. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056 Change-Id: Ie78deccb2bac51f38224e62a28dd733cefd63ed7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48883 Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
39 lines
1.5 KiB
Python
39 lines
1.5 KiB
Python
def upgrader(cpt):
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"""
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Update the checkpoint to support initial SVE implemtation.
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The updater is taking the following steps.
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1) Set isa.haveSVE to false
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2) Set isa.sveVL to 1
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3) Add SVE misc registers in the checkpoint
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"""
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if cpt.get('root', 'isa', fallback='') == 'arm':
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for sec in cpt.sections():
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import re
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# Search for all ISA sections
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if re.search('.*sys.*\.cpu.*\.isa$', sec):
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# haveSVE = false
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cpt.set(sec, 'haveSVE', 'false')
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# sveVL (sve Vector Length in quadword) = 1
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# (This is a dummy value since haveSVE is set to false)
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cpt.set(sec, 'sveVL', '1')
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# Updating SVE misc registers (dummy values)
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mr = cpt.get(sec, 'miscRegs').split()
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if len(mr) == 820:
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print("MISCREG_SVE registers already seems "
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"to be inserted.")
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else:
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# Replace MISCREG_FREESLOT_1 with MISCREG_ID_AA64ZFR0_EL1
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mr[-1] = 0;
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mr.append(0); # Add dummy value for MISCREG_ZCR_EL3
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mr.append(0); # Add dummy value for MISCREG_ZCR_EL2
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mr.append(0); # Add dummy value for MISCREG_ZCR_EL12
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mr.append(0); # Add dummy value for MISCREG_ZCR_EL1
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cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
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legacy_version = 15
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