Files
gem5/src/dev/arm
Adrien Pesle 058e2cec7c dev-arm: Add basic support for level sensitive SPIs in GICv2
For level sensitive interrupt IRQ line must be cleared when interrupt is
deasserted. This is not the case for edge-trigerred interrupt.

Change-Id: Ib1660da74a296750c0eb9e20878d4ee64bd23130
Reviewed-on: https://gem5-review.googlesource.com/12944
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01 08:28:51 +00:00
..
2017-05-31 00:20:12 +00:00
2015-03-19 04:06:17 -04:00
2015-03-19 04:06:17 -04:00
2018-09-12 10:27:06 +00:00
2015-05-13 15:02:25 +01:00
2018-09-12 10:27:06 +00:00
2015-04-23 13:37:50 -04:00