5b41112e03
The change will allow developers to implement and decode their non-standard instructions to the CPU models Bug: 289467440 Test: None Change-Id: I67f4abc71596f819c1265e325784f51c8e9bb359
88 lines
2.9 KiB
C++
88 lines
2.9 KiB
C++
/*
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* Copyright (c) 2012 Google
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* Copyright (c) 2017 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_RISCV_DECODER_HH__
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#define __ARCH_RISCV_DECODER_HH__
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#include "arch/generic/decode_cache.hh"
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#include "arch/generic/decoder.hh"
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#include "arch/riscv/insts/vector.hh"
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#include "arch/riscv/types.hh"
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#include "base/logging.hh"
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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#include "debug/Decode.hh"
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#include "params/RiscvDecoder.hh"
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namespace gem5
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{
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class BaseISA;
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namespace RiscvISA
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{
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class Decoder : public InstDecoder
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{
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private:
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decode_cache::InstMap<ExtMachInst> instMap;
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bool aligned;
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bool mid;
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protected:
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//The extended machine instruction being generated
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ExtMachInst emi;
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uint32_t machInst;
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virtual StaticInstPtr decodeInst(ExtMachInst mach_inst);
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/// Decode a machine instruction.
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/// @param mach_inst The binary instruction to decode.
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/// @retval A pointer to the corresponding StaticInst object.
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StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
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public:
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Decoder(const RiscvDecoderParams &p);
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void reset() override;
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inline bool compressed(ExtMachInst inst) { return inst.quadRant < 0x3; }
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//Use this to give data to the decoder. This should be used
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//when there is control flow.
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void moreBytes(const PCStateBase &pc, Addr fetchPC) override;
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StaticInstPtr decode(PCStateBase &nextPC) override;
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};
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} // namespace RiscvISA
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} // namespace gem5
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#endif // __ARCH_RISCV_DECODER_HH__
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