eb07d3fcf4
This changes mentions of googlesource and Gerrit to instead link to the gem5 GitHub repository, and updates the documentation to reflect the GitHub review process. Change-Id: I5dc1d9fcf6b96f9e5116802f938b7e3bb5b09567 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71878 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
115 lines
4.2 KiB
Markdown
115 lines
4.2 KiB
Markdown
# Using gem5 in an SST simulation
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## Overview
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This directory contains the library needed to use gem5 TimingSimpleCPU model in
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an SST-driven simulation.
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When compiled, the gem5 library for SST `libgem5.so` will be generated,
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containing the `libgem5_*.so` as well as the gem5 Component and the
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SST Responder SubComponent.
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```text
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On/Off-chip devs TimingSimpleCPU
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^ ^ ^
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v v v
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==================================== [gem5::NonCoherentXBar]
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^ [OutgoingRequestBridge]
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gem5_system_port |
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[OutgoingRequestBridge] ^ |
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[SSTResponder] v v [SSTResponder]
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gem5 Component {SSTResponderSubComponent, SSTResponderSubComponent}
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^ ^
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v v
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================================== [SST Bus]
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^
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v
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SST cache <----> SST memory
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```
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## Components and SubComponents
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- gem5 Component has the following responsibilities,
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- initializing the gem5 Python environment
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- instantiating/setting-up the gem5 SimObjects as specified by the gem5
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configuration
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- connect every SSTResponderSubComponent to the corresponding
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OutgoingRequestBridge
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- handling a gem5 event queue (with all thread-synchronization barriers
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removed)
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- handling executions of gem5 events when it has clockTick yielded by SST
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**Note:** there should only be one gem5 Component per process.
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- SSTResponderSubComponent has the responsibity of receiving requests from
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gem5, translating requests to an SST Request and sending it to SSTResponder.
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Upon receiving a response from the memory interface, SSTResponderSubComponent
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will translate the response to a gem5 Packet and send it to the its
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OutgoingRequestBridge.
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- SSTResponder is owned by SSTResponderSubComponent. The responder will receive
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the request from the SubComponent and send it to the SST memory hierarchy.
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## Installation
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See `INSTALL.md`.
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## Running an example simulation (RISCV)
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Downloading the built bootloader containing a Linux Kernel and a workload,
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```sh
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wget http://dist.gem5.org/dist/develop/misc/riscv/bbl-busybox-boot-exit
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```
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Running the simulation
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```sh
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sst --add-lib-path=./ sst/example.py
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```
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The example SST system configuration will instantiate the gem5 system
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as specified in the gem5 system configuration located at
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`gem5/configs/example/sst/riscv_fs.py`. This configuration will download
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the `bbl-busybox-boot-exit` resource, which contains an m5 binary, and
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`m5 exit` will be called upon the booting process reaching the early userspace.
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More information about building a bootloader containing a Linux Kernel and a
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customized workload is available at
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[https://github.com/gem5/gem5-resources/tree/stable/src/riscv-boot-exit-nodisk].
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## Running an example simulation (Arm)
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Download the prebuilt bootloader and Linux Kernel with embedded initramfs and
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extract them under the $M5_PATH directory (make sure M5_PATH points to a valid
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directory):
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```sh
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wget http://dist.gem5.org/dist/develop/arm/aarch-sst-20211207.tar.bz2
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tar -xf aarch-sst-20211207.tar.bz2
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# copying bootloaders
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cp binaries/boot* $M5_PATH/binaries/
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# copying Linux Kernel
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cp binaries/vmlinux_exit.arm64 $M5_PATH/binaries/
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```
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`vmlinux_exit.arm64` contains an m5 binary, and `m5 exit` will be called upon
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the booting process reaching the early userspace.
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Run the simulation:
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```sh
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sst sst/arm_example.py
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```
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## Notes
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- SwapReq from gem5 requires reading from memory and writing to memory.
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We handle the request in SST in a way that, when SST gets the response
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from memory, SST will send that response to gem5, while SST will send
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a write request with modified data to memory.
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