First PIM modifications

Recent breaking changes in the DRAMSys API require user code to be
updated. These updates have been applied to the gem5 integration.

Furthermore, as DRAMSys started to use CMake dependency management,
it is no longer sensible to maintain two separate build systems for
DRAMSys. The use of the DRAMSys integration in gem5 will therefore
from now on require that CMake is installed on the target machine.

Additionally, support for snapshots have been implemented into DRAMSys
and coupled with gem5's checkpointing API.

Change-Id: I1ab25deba2a8478ff97c477694813ac123d60379

.devcontainer/devcontainer.json

@@ -1,37 +0,0 @@
-{
-    "name": "gem5 Development Container",
-    "image": "ghcr.io/gem5/devcontainer:latest",
-    "hostRequirements": {
-        "cpus": 8,
-        "memory": "16gb",
-        "storage": "32gb"
-     },
-    "customizations": {
-        "vscode": {
-            "extensions": [
-                "eamodio.gitlens",
-                "GitHub.copilot",
-                "GitHub.copilot-chat",
-                "GitHub.vscode-pull-request-github",
-                "ms-python.debugpy",
-                "ms-python.isort",
-                "ms-python.python",
-                "ms-python.vscode-pylance",
-                "ms-vscode.cpptools",
-                "ms-vscode.cpptools-extension-pack",
-                "ms-vscode.cpptools-themes",
-                "ms-vscode.makefile-tools",
-                "ms-vscode-remote.remote-containers",
-                "Tsinghua-Hexin-Joint-Institute.gem5-slicc",
-                "VisualStudioExptTeam.vscodeintellicode"
-            ]
-        }
-    },
-    "features": {
-        "ghcr.io/devcontainers/features/docker-in-docker:2": {},
-        "ghcr.io/devcontainers/features/github-cli:1": {},
-        "ghcr.io/devcontainers-contrib/features/actionlint:1": {},
-        "ghcr.io/devcontainers-contrib/features/vscode-cli:1": {}
-    },
-    "onCreateCommand": "./.devcontainer/on-create.sh"
-}

.git-blame-ignore-revs

@@ -29,9 +29,3 @@ c3bd8eb1214cbebbc92c7958b80aa06913bce3ba
 
 # A commit which ran flynt all Python files.
 e73655d038cdfa68964109044e33c9a6e7d85ac9
-
-# A commit which ran pre-commit on ext/testlib
-9e1afdecefaf910fa6e266f29dc480a32b0fa83e
-
-# Updated black from 22.6.0 to 23.9.1
-ddf6cb88e48df4ac7de4a9e4b612daf2e7e635c8

.github/dependabot.yml

@@ -1,17 +0,0 @@
----
-version: 2
-updates:
-    - package-ecosystem: pip
-      directory: /
-      schedule:
-          interval: monthly
-      assignees:
-          - Harshil2107
-      commit-message:
-          prefix: 'misc: '
-    # Raise pull requests for version updates
-    # to pip against the `develop` branch
-      target-branch: develop
-    # Labels on pull requests for version updates only
-      labels:
-          - misc

.github/workflows/ci-tests.yaml

@@ -5,7 +5,7 @@ name: CI Tests
 
 on:
     pull_request:
-        types: [opened, synchronize, ready_for_review]
+        types: [opened, edited, synchronize, ready_for_review]
 
 concurrency:
     group: ${{ github.workflow }}-${{ github.ref || github.run_id }}
@@ -14,55 +14,50 @@ concurrency:
 jobs:
     pre-commit:
     # runs on github hosted runner
-        runs-on: ubuntu-latest
+        runs-on: ubuntu-22.04
         if: github.event.pull_request.draft == false
         steps:
-            - uses: actions/checkout@v4
-            - uses: actions/setup-python@v5
-            - uses: pre-commit/action@v3.0.1
+            - uses: actions/checkout@v3
+            - uses: actions/setup-python@v3
+            - uses: pre-commit/action@v3.0.0
 
-    get-date:
-    # We use the date to label caches. A cache is a a "hit" if the date is the
-    # request binary and date are the same as what is stored in the cache.
-    # This essentially means the first job to run on a given day for a given
-    # binary will always be a "miss" and will have to build the binary then
-    # upload it as that day's binary to upload. While this isn't the most
-    # efficient way to do this, the alternative was to run take a hash of the
-    # `src` directory contents and use it as a hash. We found there to be bugs
-    # with the hash function where this task would timeout. This approach is
-    # simple, works, and still provides some level of caching.
-        runs-on: ubuntu-latest
-        outputs:
-            date: ${{ steps.date.outputs.date }}
+  # ensures we have a change-id in every commit, needed for gerrit
+    check-for-change-id:
+        # runs on github hosted runner
+        runs-on: ubuntu-22.04
+        if: github.event.pull_request.draft == false
         steps:
-            - name: Get the current date
-              id: date
-              run: echo "date=$(date +'%Y-%m-%d')" >> $GITHUB_ENV
+            - uses: actions/checkout@v3
+              with:
+                  fetch-depth: 0
+            - name: Check for Change-Id
+              run: |
+                  # loop through all the commits in the pull request
+                  for commit in $(git rev-list ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}); do
+                      git checkout $commit
+                      if (git log -1 --pretty=format:"%B" | grep -q "Change-Id: ")
+                      then
+                        # passes as long as at least one change-id exists in the pull request
+                        exit 0
+                      fi
+                  done
+                  # if we reach this part, none of the commits had a change-id
+                  echo "None of the commits in this pull request contains a Change-ID, which we require for any changes made to gem5. "\
+                    "To automatically insert one, run the following:\n f=`git rev-parse --git-dir`/hooks/commit-msg ; mkdir -p $(dirname $f) ; "\
+                    "curl -Lo $f https://gerrit-review.googlesource.com/tools/hooks/commit-msg ; chmod +x $f\n Then amend the commit with git commit --amend --no-edit, and update your pull request."
+                  exit 1
 
     unittests-all-opt:
         runs-on: [self-hosted, linux, x64]
         if: github.event.pull_request.draft == false
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
-        needs: [pre-commit, get-date] # only runs if pre-commit passes.
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
+        needs: [pre-commit, check-for-change-id] # only runs if pre-commit and change-id passes
         timeout-minutes: 60
         steps:
-            - uses: actions/checkout@v4
-
-
-            # Restore the cache if available. As this just builds the unittests
-            # we only obtain the cache and do not provide if if is not
-            # available.
-            - name: Cache build/ALL
-              uses: actions/cache/restore@v4
-              with:
-                  path: build/ALL
-                  key: testlib-build-all-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-all
-
+            - uses: actions/checkout@v3
             - name: CI Unittests
               working-directory: ${{ github.workspace }}
-              run: scons --no-compress-debug build/ALL/unittests.opt -j $(nproc)
+              run: scons build/ALL/unittests.opt -j $(nproc)
             - run: echo "This job's status is ${{ job.status }}."
 
     testlib-quick-matrix:
@@ -70,15 +65,15 @@ jobs:
         if: github.event.pull_request.draft == false
     # In order to make sure the environment is exactly the same, we run in
     # the same container we use to build gem5 and run the testlib tests. This
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
-        needs: [pre-commit]
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
+        needs: [pre-commit, check-for-change-id]
         steps:
-            - uses: actions/checkout@v4
+            - uses: actions/checkout@v3
 
-            # Unfortunately the image doesn't have jq installed.
-            # We therefore need to install it as a step here.
+      # Unfortunately the 'ubunutu-latest' image doesn't have jq installed.
+      # We therefore need to install it as a step here.
             - name: Install jq
-              run: apt update && apt install -y jq
+              run: apt install -y jq
 
             - name: Get directories for testlib-quick
               working-directory: ${{ github.workspace }}/tests
@@ -94,44 +89,18 @@ jobs:
             build-matrix: ${{ steps.build-matrix.outputs.build-matrix }}
             test-dirs-matrix: ${{ steps.dir-matrix.outputs.test-dirs-matrix }}
 
-    clang-fast-compilation:
-        # gem5 binaries built in `quick-gem5-builds` always use GCC.
-        # Clang is more strict than GCC. This job checks that gem5 compiles
-        # with Clang. It compiles build/ALL/gem5.fast to maximize the change
-        # for compilation error to be exposed.
-        runs-on: [self-hosted, linux, x64]
-        if: github.event.pull_request.draft == false
-        container: ghcr.io/gem5/clang-version-18:latest
-        needs: [pre-commit]
-        timeout-minutes: 90
-        steps:
-            - uses: actions/checkout@v4
-            - name: Clang Compilation
-              working-directory: ${{ github.workspace }}
-              run: scons build/ALL/gem5.fast -j $(nproc)
-
     testlib-quick-gem5-builds:
         runs-on: [self-hosted, linux, x64]
         if: github.event.pull_request.draft == false
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
-        needs: [pre-commit, testlib-quick-matrix, get-date]
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
+        needs: [pre-commit, check-for-change-id, testlib-quick-matrix]
         strategy:
             matrix:
                 build-target: ${{ fromJson(needs.testlib-quick-matrix.outputs.build-matrix) }}
         steps:
-            - uses: actions/checkout@v4
-
-            - name: Cache build/ALL
-              uses: actions/cache@v4
-              if: ${{ endsWith(matrix.build-target, 'build/ALL/gem5.opt') }}
-              with:
-                  path: build/ALL
-                  key: testlib-build-all-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-all
-
+            - uses: actions/checkout@v3
             - name: Build gem5
-              run: scons --no-compress-debug ${{ matrix.build-target }} -j $(nproc)
+              run: scons ${{ matrix.build-target }} -j $(nproc)
 
         # Upload the gem5 binary as an artifact.
         # Note: the "achor.txt" file is a hack to make sure the paths are
@@ -142,7 +111,7 @@ jobs:
         # stripping the "build" directory. By adding the "anchor.txt" file, we
         # ensure the "build" directory is preserved.
             - run: echo "anchor" > anchor.txt
-            - uses: actions/upload-artifact@v4
+            - uses: actions/upload-artifact@v3
               with:
                   name: ci-tests-${{ github.run_number }}-testlib-quick-all-gem5-builds
                   path: |
@@ -153,8 +122,8 @@ jobs:
     testlib-quick-execution:
         runs-on: [self-hosted, linux, x64]
         if: github.event.pull_request.draft == false
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
-        needs: [pre-commit, testlib-quick-matrix, testlib-quick-gem5-builds]
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
+        needs: [pre-commit, check-for-change-id, testlib-quick-matrix, testlib-quick-gem5-builds]
         timeout-minutes: 360 # 6 hours
         strategy:
             fail-fast: false
@@ -165,8 +134,8 @@ jobs:
               run: rm -rf ./* || true rm -rf ./.??* || true rm -rf ~/.cache || true
 
         # Checkout the repository then download the gem5.opt artifact.
-            - uses: actions/checkout@v4
-            - uses: actions/download-artifact@v4
+            - uses: actions/checkout@v3
+            - uses: actions/download-artifact@v3
               with:
                   name: ci-tests-${{ github.run_number }}-testlib-quick-all-gem5-builds
 
@@ -190,98 +159,21 @@ jobs:
               run: echo "sanatized-test-dir=$(echo '${{ matrix.test-dir }}' | sed 's/\//-/g')" >> $GITHUB_OUTPUT
 
         # Upload the tests/testing-results directory as an artifact.
-            - name: upload results
+            - name: Upload test results
               if: success() || failure()
-              uses: actions/upload-artifact@v4
+              uses: actions/upload-artifact@v3
               with:
                   name: ci-tests-run-${{ github.run_number }}-attempt-${{ github.run_attempt }}-testlib-quick-${{ steps.sanitize-test-dir.outputs.sanatized-test-dir
                       }}-status-${{ steps.run-tests.outcome }}-output
                   path: tests/testing-results
                   retention-days: 30
 
-    pyunit:
-        runs-on: [self-hosted, linux, x64]
-        if: github.event.pull_request.draft == false
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
-        needs: [pre-commit, testlib-quick-gem5-builds]
-        timeout-minutes: 30
-        steps:
-
-            # Checkout the repository then download the builds.
-            - uses: actions/checkout@v4
-            - uses: actions/download-artifact@v4
-              with:
-                  name: ci-tests-${{ github.run_number }}-testlib-quick-all-gem5-builds
-
-            # Check that the gem5 binaries exist and are executable.
-            - name: Chmod gem5.{opt,debug,fast} to be executable
-              run: |
-                  find . -name "gem5.opt" -exec chmod u+x {} \;
-                  find . -name "gem5.debug" -exec chmod u+x {} \;
-                  find . -name "gem5.fast" -exec chmod u+x {} \;
-
-            # Run the pyunit tests.
-            # Note: these are all quick tests.
-            - name: Run The pyunit tests
-              id: run-tests
-              working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run --skip-build -vv -j$(nproc) pyunit
-
-            # Upload the tests/testing-results directory as an artifact.
-            - name: Upload pyunit test results
-              if: success() || failure()
-              uses: actions/upload-artifact@v4
-              with:
-                  name: ci-tests-run-${{ github.run_number }}-attempt-${{ github.run_attempt }}-pyunit-status-${{ steps.run-tests.outcome }}-output
-                  path: tests/testing-results
-                  retention-days: 30
-
-    gpu-tests:
-        runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/gcn-gpu:latest
-        timeout-minutes: 180
-        needs: [pre-commit, get-date]
-        steps:
-            - uses: actions/checkout@v4
-
-            # Obtain the cache if available. If not available this will upload
-            # this job's instance of the cache.
-            - name: Cache build/VEGA_X86
-              uses: actions/cache@v4
-              with:
-                  path: build/VEGA_X86
-                  key: testlib-build-vega-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-vega
-
-            # Build the VEGA_X86/gem5.opt binary.
-            - name: Build VEGA_X86/gem5.opt
-              run: scons --no-compress-debug build/VEGA_X86/gem5.opt -j`nproc`
-
-            # Run the GPU tests.
-            - name: Run Testlib GPU Tests
-              working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run  --skip-build -vvv -t $(nproc) --host gcn_gpu gem5/gpu
-
-            # Upload the tests/testing-results directory as an artifact.
-            - name: Upload results
-              if: success() || failure()
-              uses: actions/upload-artifact@v4
-              with:
-                  name: ci-tests-run-${{ github.run_number }}-attempt-${{ github.run_attempt }}-gpu-status-${{ steps.run-tests.outcome }}-output
-                  path: tests/testing-results
-                  retention-days: 30
-
-    ci-tests:
+    testlib-quick:
     # It is 'testlib-quick' which needs to pass for the pull request to be
-    # merged. This job is a dummy job that depends on all the other jobs.
-        runs-on: ubuntu-latest
-        needs:
-            - testlib-quick-execution
-            - pyunit
-            - clang-fast-compilation
-            - unittests-all-opt
-            - pre-commit
-            - gpu-tests
+    # merged. The 'testlib-quick-execution' is a matrix job which runs all the
+    # the testlib quick tests. This job is therefore a stub which will pass if
+    # all the testlib-quick-execution jobs pass.
+        runs-on: ubuntu-22.04
+        needs: testlib-quick-execution
         steps:
             - run: echo "This job's status is ${{ job.status }}."

.github/workflows/compiler-tests.yaml

@@ -4,7 +4,10 @@
 name: Compiler Tests
 
 on:
-    # This is triggered weekly via the 'scheduler.yaml' workflow.
+  # Runs every Friday from 7AM UTC
+    schedule:
+        - cron: 00 7 * * 5
+  # Allows us to manually start workflow for testing
     workflow_dispatch:
 
 jobs:
@@ -13,14 +16,19 @@ jobs:
         strategy:
             fail-fast: false
             matrix:
-                image: [gcc-version-14, gcc-version-13, gcc-version-12, gcc-version-11, gcc-version-10, clang-version-18, clang-version-17, clang-version-16,
-                    clang-version-15, clang-version-14, ubuntu-22.04_all-dependencies, ubuntu-24.04_all-dependencies, ubuntu-24.04_min-dependencies]
+                image: [gcc-version-12, gcc-version-11, gcc-version-10, gcc-version-9, gcc-version-8, clang-version-16, clang-version-15, clang-version-14,
+                    clang-version-13, clang-version-12, clang-version-11, clang-version-10, clang-version-9, clang-version-8, clang-version-7, ubuntu-20.04_all-dependencies,
+                    ubuntu-22.04_all-dependencies, ubuntu-22.04_min-dependencies]
                 opts: [.opt, .fast]
         runs-on: [self-hosted, linux, x64]
         timeout-minutes: 2880 # 48 hours
         container: ghcr.io/gem5/${{ matrix.image }}:latest
         steps:
-            - uses: actions/checkout@v4
+            - uses: actions/checkout@v3
+              with:
+        # Scheduled workflows run on the default branch by default. We
+        # therefore need to explicitly checkout the develop branch.
+                  ref: develop
             - name: Compile build/ALL/gem5${{ matrix.opts }} with ${{ matrix.image }}
               run: /usr/bin/env python3 /usr/bin/scons --ignore-style build/ALL/gem5${{ matrix.opts }} -j$(nproc)
               timeout-minutes: 600 # 10 hours
@@ -30,15 +38,20 @@ jobs:
         strategy:
             fail-fast: false
             matrix:
-                gem5-compilation: [ARM, ARM_MESI_Three_Level, ARM_MESI_Three_Level_HTM, ARM_MOESI_hammer, Garnet_standalone, MIPS, 'NULL', NULL_MESI_Two_Level,
-                    NULL_MOESI_CMP_directory, NULL_MOESI_CMP_token, NULL_MOESI_hammer, POWER, RISCV, SPARC, X86, X86_MI_example, X86_MOESI_AMD_Base, VEGA_X86]
-                image: [gcc-version-14, clang-version-18]
+                gem5-compilation: [ARM, ARM_MESI_Three_Level, ARM_MESI_Three_Level_HTM, ARM_MOESI_hammer, Garnet_standalone, GCN3_X86, MIPS, 'NULL', NULL_MESI_Two_Level,
+                    NULL_MOESI_CMP_directory, NULL_MOESI_CMP_token, NULL_MOESI_hammer, POWER, RISCV, SPARC, X86, X86_MI_example, X86_MOESI_AMD_Base, VEGA_X86,
+                    GCN3_X86]
+                image: [gcc-version-12, clang-version-16]
                 opts: [.opt]
         runs-on: [self-hosted, linux, x64]
         timeout-minutes: 2880 # 48 hours
         container: ghcr.io/gem5/${{ matrix.image }}:latest
         steps:
-            - uses: actions/checkout@v4
+            - uses: actions/checkout@v3
+              with:
+        # Scheduled workflows run on the default branch by default. We
+        # therefore need to explicitly checkout the develop branch.
+                  ref: develop
             - name: Compile build/${{ matrix.gem5-compilation }}/gem5${{ matrix.opts }} with ${{ matrix.image }}
               run: /usr/bin/env python3 /usr/bin/scons --ignore-style build/${{ matrix.gem5-compilation }}/gem5${{ matrix.opts }} -j$(nproc)
               timeout-minutes: 600 # 10 hours
@@ -49,7 +62,7 @@ jobs:
         # I.e., if we want to stop pull requests from being merged if the
         # compiler tests are failing, we can add this job as a required status
         # check.
-        runs-on: ubuntu-latest
+        runs-on: ubuntu-22.04
         needs:
             - latest-compilers-all-gem5-builds
             - all-compilers

.github/workflows/daily-tests.yaml

@@ -4,19 +4,56 @@
 name: Daily Tests
 
 on:
-    # This is triggered weekly via the 'scheduler.yaml' workflow.
-    workflow_dispatch:
+  # Runs every day from 7AM UTC
+    schedule:
+        - cron: 0 7 * * *
 
 jobs:
-
-    get-date:
+    name-artifacts:
         runs-on: ubuntu-latest
         outputs:
-            date: ${{ steps.date.outputs.date }}
+            build-name: ${{ steps.artifact-name.outputs.name }}
         steps:
-            - name: Get the current date
-              id: date
-              run: echo "date=$(date +'%Y-%m-%d')" >> $GITHUB_ENV
+            - uses: actions/checkout@v2
+            - id: artifact-name
+              run: echo "name=$(date +"%Y-%m-%d_%H.%M.%S-")" >> $GITHUB_OUTPUT
+
+    build-gem5:
+        strategy:
+            fail-fast: false
+            matrix:
+        # NULL is in quotes since it is considered a keyword in yaml files
+                image: [ALL, ALL_CHI, ARM, ALL_MSI, ALL_MESI_Two_Level, 'NULL', NULL_MI_example, RISCV, VEGA_X86]
+        # this allows us to pass additional command line parameters
+        # the default is to add -j $(nproc), but some images
+        # require more specifications when built
+                include:
+                    - command-line: -j $(nproc)
+                    - image: ALL_CHI
+                      command-line: --default=ALL PROTOCOL=CHI -j $(nproc)
+                    - image: ALL_MSI
+                      command-line: --default=ALL PROTOCOL=MSI -j $(nproc)
+                    - image: ALL_MESI_Two_Level
+                      command-line: --default=ALL PROTOCOL=MESI_Two_Level -j $(nproc)
+                    - image: NULL_MI_example
+                      command-line: --default=NULL PROTOCOL=MI_example -j $(nproc)
+        runs-on: [self-hosted, linux, x64]
+        needs: name-artifacts
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
+        steps:
+            - uses: actions/checkout@v3
+              with:
+          # Scheduled workflows run on the default branch by default. We
+          # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+            - name: Build gem5
+              run: scons build/${{ matrix.image }}/gem5.opt ${{ matrix.command-line }}
+            - uses: actions/upload-artifact@v3
+              with:
+                  name: ${{ needs.name-artifacts.outputs.build-name }}${{ matrix.image }}
+                  path: build/${{ matrix.image }}/gem5.opt
+                  retention-days: 5
+            - run: echo "This job's status is ${{ job.status }}."
 
   # this builds both unittests.fast and unittests.debug
     unittests-fast-debug:
@@ -24,18 +61,14 @@ jobs:
             matrix:
                 type: [fast, debug]
         runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
         timeout-minutes: 60
-        needs: get-date
         steps:
-            - uses: actions/checkout@v4
-            - name: Cache build/ALL
-              uses: actions/cache/restore@v4
+            - uses: actions/checkout@v3
               with:
-                  path: build/ALL
-                  key: testlib-build-all-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-all
+          # Scheduled workflows run on the default branch by default. We
+          # therefore need to explicitly checkout the develop branch.
+                  ref: develop
             - name: ALL/unittests.${{ matrix.type }} UnitTests
               run: scons build/ALL/unittests.${{ matrix.type }} -j $(nproc)
 
@@ -44,42 +77,87 @@ jobs:
         strategy:
             fail-fast: false
             matrix:
-                test-type: [arm_boot_tests, fs, gpu, insttest_se, learning_gem5, m5threads_test_atomic, memory, replacement_policies, riscv_boot_tests,
+                test-type: [arm_boot_tests, fs, gpu, insttest_se, learning_gem5, m5threads_test_atomic, memory, multi_isa, replacement_policies, riscv_boot_tests,
                     stdlib, x86_boot_tests]
         runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
+        needs: [name-artifacts, build-gem5]
         timeout-minutes: 1440 # 24 hours for entire matrix to run
-        needs: get-date
         steps:
             - name: Clean runner
               run: rm -rf ./* || true rm -rf ./.??* || true rm -rf ~/.cache || true
-            - uses: actions/checkout@v4
-
-            - name: Restore build/NULL cache
-              uses: actions/cache@v4
+            - uses: actions/checkout@v3
               with:
-                  path: build/NULL
-                  key: testlib-build-null-${{ needs.get-date.outputs.date }}
-
-            - name: Restore build/ALL cache
-              uses: actions/cache@v4
+        # Scheduled workflows run on the default branch by default. We
+        # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+    # download all artifacts for each test
+    # since long tests can't start until the build matrix completes,
+    # we download all artifacts from the build for each test
+    # in this matrix
+            - uses: actions/download-artifact@v3
               with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}ALL
                   path: build/ALL
-                  key: testlib-build-all-${{ needs.get-date.outputs.date }}
-
+            - run: chmod u+x build/ALL/gem5.opt
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}ALL_CHI
+                  path: build/ALL_CHI
+            - run: chmod u+x build/ALL_CHI/gem5.opt
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}ARM
+                  path: build/ARM
+            - run: chmod u+x build/ARM/gem5.opt
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}ALL_MSI
+                  path: build/ALL_MSI
+            - run: chmod u+x build/ALL_MSI/gem5.opt
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}ALL_MESI_Two_Level
+                  path: build/ALL_MESI_Two_Level
+            - run: chmod u+x build/ALL_MESI_Two_Level/gem5.opt
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}NULL
+                  path: build/NULL
+            - run: chmod u+x build/NULL/gem5.opt
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}NULL_MI_example
+                  path: build/NULL_MI_example
+            - run: chmod u+x build/NULL_MI_example/gem5.opt
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}RISCV
+                  path: build/RISCV
+            - run: chmod u+x build/RISCV/gem5.opt
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}VEGA_X86
+                  path: build/VEGA_X86
+            - run: chmod u+x build/VEGA_X86/gem5.opt
+    # run test
             - name: long ${{ matrix.test-type }} tests
               working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run gem5/${{ matrix.test-type }} -j$(nproc) --length=long -vv -t $(nproc)
-            - name: upload results
+              run: ./main.py run gem5/${{ matrix.test-type }} --length=long --skip-build -vv -t $(nproc)
+            - name: create zip of results
               if: success() || failure()
-              uses: actions/upload-artifact@v4
+              run: |
+                  apt-get -y install zip
+                  zip -r output.zip tests/testing-results
+            - name: upload zip
+              if: success() || failure()
+              uses: actions/upload-artifact@v3
               env:
                   MY_STEP_VAR: ${{ matrix.test-type }}_COMMIT.${{github.sha}}_RUN.${{github.run_id}}_ATTEMPT.${{github.run_attempt}}
               with:
                   name: ${{ env.MY_STEP_VAR }}
-                  path: tests/testing-results
+                  path: output.zip
                   retention-days: 7
-
             - run: echo "This job's status is ${{ job.status }}."
 
   # split library example tests into runs based on Suite UID
@@ -91,72 +169,42 @@ jobs:
             matrix:
                 test-type: [gem5-library-example-x86-ubuntu-run-ALL-x86_64-opt, gem5-library-example-riscv-ubuntu-run-ALL-x86_64-opt, lupv-example-ALL-x86_64-opt,
                     gem5-library-example-arm-ubuntu-run-test-ALL-x86_64-opt, gem5-library-example-riscvmatched-hello-ALL-x86_64-opt]
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
+        needs: [name-artifacts, build-gem5]
         timeout-minutes: 1440 # 24 hours
-        needs: get-date
         steps:
             - name: Clean runner
               run: rm -rf ./* || true rm -rf ./.??* || true rm -rf ~/.cache || true
-            - uses: actions/checkout@v4
-
-            - name: Cache build/ALL
-              uses: actions/cache@v4
+            - uses: actions/checkout@v3
               with:
+        # Scheduled workflows run on the default branch by default. We
+        # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.name-artifacts.outputs.build-name}}ALL
                   path: build/ALL
-                  key: testlib-build-all-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-all
-
+            - run: chmod u+x build/ALL/gem5.opt
             - name: long ${{ matrix.test-type }} gem5_library_example_tests
               working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run --uid SuiteUID:tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py:test-${{ matrix.test-type }} -j $(nproc)
-                  --length=long -vv
-            - name: upload results
+              run: ./main.py run --uid SuiteUID:tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py:test-${{ matrix.test-type }} --length=long
+                  --skip-build -vv
+            - name: create zip of results
               if: success() || failure()
-              uses: actions/upload-artifact@v4
+              run: |
+                  apt-get -y install zip
+                  zip -r output.zip tests/testing-results
+            - name: upload zip
+              if: success() || failure()
+              uses: actions/upload-artifact@v3
               env:
                   MY_STEP_VAR: ${{ matrix.test-type }}_COMMIT.${{github.sha}}_RUN.${{github.run_id}}_ATTEMPT.${{github.run_attempt}}
               with:
                   name: ${{ env.MY_STEP_VAR }}
-                  path: tests/testing-results
+                  path: output.zip
                   retention-days: 7
             - run: echo "This job's status is ${{ job.status }}."
 
-    gpu-tests:
-        runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/gcn-gpu:latest
-        timeout-minutes: 720 # 12 hours
-        needs: get-date
-
-        steps:
-            - uses: actions/checkout@v4
-              with:
-                  ref: develop
-
-            - name: Cache build/VEGA_X86
-              uses: actions/cache@v4
-              with:
-                  path: build/VEGA_X86
-                  key: testlib-build-vega-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-vega
-
-            - name: Build VEGA_X86/gem5.opt
-              working-directory: ${{ github.workspace }}
-              run: scons build/VEGA_X86/gem5.opt -j $(nproc)
-
-            - name: Run Testlib GPU Tests
-              working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run --length=long -vvv --skip-build -t $(nproc) --host gcn_gpu  gem5/gpu
-
-            - name: Upload results
-              if: success() || failure()
-              uses: actions/upload-artifact@v4
-              with:
-                  name: gpu_tests_${{github.sha}}_RUN_${{github.run_id}}_ATTEMPT_${{github.run_attempt}}
-                  path: tests/testing-results
-                  retention-days: 7
-
   # This runs the SST-gem5 integration compilation and tests it with
   # ext/sst/sst/example.py.
     sst-test:
@@ -165,7 +213,11 @@ jobs:
         timeout-minutes: 180
 
         steps:
-            - uses: actions/checkout@v4
+            - uses: actions/checkout@v3
+              with:
+        # Scheduled workflows run on the default branch by default. We
+        # therefore need to explicitly checkout the develop branch.
+                  ref: develop
             - name: Build RISCV/libgem5_opt.so with SST
               run: scons build/RISCV/libgem5_opt.so --without-tcmalloc --duplicate-sources --ignore-style -j $(nproc)
             - name: Makefile ext/sst
@@ -186,13 +238,15 @@ jobs:
         timeout-minutes: 180
 
         steps:
-            - uses: actions/checkout@v4
+            - uses: actions/checkout@v3
+              with:
+        # Scheduled workflows run on the default branch by default. We
+        # therefore need to explicitly checkout the develop branch.
+                  ref: develop
             - name: Build ARM/gem5.opt
               run: scons build/ARM/gem5.opt --ignore-style --duplicate-sources -j$(nproc)
-            - name: disable systemc
-              run: scons setconfig build/ARM --ignore-style USE_SYSTEMC=n
             - name: Build ARM/libgem5_opt.so
-              run: scons build/ARM/libgem5_opt.so --with-cxx-config --without-python --without-tcmalloc -j$(nproc) --duplicate-sources
+              run: scons build/ARM/libgem5_opt.so --with-cxx-config --without-python --without-tcmalloc USE_SYSTEMC=0 -j$(nproc) --duplicate-sources
             - name: Compile gem5 withing SystemC
               working-directory: ${{ github.workspace }}/util/systemc/gem5_within_systemc
               run: make
@@ -201,13 +255,45 @@ jobs:
             - name: Continue gem5 within SystemC test
               run: LD_LIBRARY_PATH=build/ARM/:/opt/systemc/lib-linux64/ ./util/systemc/gem5_within_systemc/gem5.opt.sc m5out/config.ini
 
+  # Runs the gem5 Nighyly GPU tests.
+    gpu-tests:
+        runs-on: [self-hosted, linux, x64]
+        container: ghcr.io/gem5/gcn-gpu:latest
+        timeout-minutes: 720 # 12 hours
+
+        steps:
+            - uses: actions/checkout@v3
+              with:
+        # Scheduled workflows run on the default branch by default. We
+        # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+            - name: Compile build/GCN3_X86/gem5.opt
+              run: scons build/GCN3_X86/gem5.opt -j $(nproc)
+            - name: Get Square test-prog from gem5-resources
+              uses: wei/wget@v1
+              with:
+                  args: -q http://dist.gem5.org/dist/develop/test-progs/square/square # Removed -N bc it wasn't available within actions, should be okay bc workspace is clean every time: https://github.com/coder/sshcode/issues/102
+            - name: Run Square test with GCN3_X86/gem5.opt (SE mode)
+              run: |
+                  mkdir -p tests/testing-results
+                  ./build/GCN3_X86/gem5.opt configs/example/apu_se.py --reg-alloc-policy=dynamic -n3 -c square
+            - name: Get allSyncPrims-1kernel from gem5-resources
+              uses: wei/wget@v1
+              with:
+                  args: -q http://dist.gem5.org/dist/develop/test-progs/heterosync/gcn3/allSyncPrims-1kernel # Removed -N bc it wasn't available within actions, should be okay bc workspace is clean every time
+            - name: Run allSyncPrims-1kernel sleepMutex test with GCN3_X86/gem5.opt (SE mode)
+              run: ./build/GCN3_X86/gem5.opt configs/example/apu_se.py --reg-alloc-policy=dynamic -n3 -c allSyncPrims-1kernel --options="sleepMutex 10 16
+                  4"
+            - name: Run allSyncPrims-1kernel lfTreeBarrUsing test with GCN3_X86/gem5.opt (SE mode)
+              run: ./build/GCN3_X86/gem5.opt configs/example/apu_se.py --reg-alloc-policy=dynamic -n3 -c allSyncPrims-1kernel --options="lfTreeBarrUniq
+                  10 16 4"
     daily-tests:
         # The dummy job is used to indicate whether the daily tests have
         # passed or not. This can be used as status check for pull requests.
         # I.e., if we want to stop pull requests from being merged if the
         # daily tests are failing we can add this job as a required status
         # check.
-        runs-on: ubuntu-latest
+        runs-on: ubuntu-22.04
         needs:
             - unittests-fast-debug
             - testlib-long-tests

.github/workflows/docker-build.yaml

@@ -1,65 +1,54 @@
 ---
 name: Docker images build and push
 
-#on:
-#  push:
-#    branches:
-#      - 'develop'
-#    paths:
-#      - util/dockerfiles/**
 on:
     workflow_dispatch:
-
-
 jobs:
-
-    obtain-targets:
-        runs-on: ubuntu-latest
-        outputs:
-            targets: ${{ steps.generate.outputs.targets }}
+    obtain-dockerfiles:
+        runs-on: [self-hosted, linux, x64]
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
 
         steps:
-            - name: Checkout
-              uses: actions/checkout@v4
-
-            - name: List targets
-              id: generate
-              uses: docker/bake-action/subaction/list-targets@v4
+            - uses: actions/checkout@v3
               with:
-                  target: default
-                  workdir: util/dockerfiles
+          # Scheduled workflows run on the default branch by default. We
+          # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+            - uses: actions/upload-artifact@v3
+              with:
+                  name: dockerfiles
+                  path: util/dockerfiles
 
-    docker-buildx-bake:
+  # This builds and pushes the docker image.
+    build-and-push:
         runs-on: [self-hosted, linux, x64]
-        needs:
-            - obtain-targets
-
-        strategy:
-            fail-fast: false
-            matrix:
-                target: ${{ fromJson(needs.obtain-targets.outputs.targets) }}
-
+        needs: obtain-dockerfiles
         permissions:
             packages: write
             contents: read
 
         steps:
-            - name: Checkout
-              uses: actions/checkout@v4
+            - uses: actions/download-artifact@v3
+              with:
+                  name: dockerfiles
+                  path: dockerfiles-docker-build
 
-            - name: Set up Docker Buildx
-              uses: docker/setup-buildx-action@v3
+            - uses: docker/setup-qemu-action@v2
+              name: Setup QEMU
 
-            - name: Login to GitHub Container Registry
-              uses: docker/login-action@v3
+            - uses: docker/setup-buildx-action@v2
+              name: Set up Docker Buildx
+
+            - uses: docker/login-action@v2
+              name: Login to the GitHub Container Registry
               with:
                   registry: ghcr.io
-                  username: ${{ github.actor }}
+                  username: ${{ github.repository_owner }}
                   password: ${{ secrets.GITHUB_TOKEN }}
 
-            - name: Build and push
-              uses: docker/bake-action@v5
+            - name: Build and push with bake
+              uses: docker/bake-action@v4
               with:
-                  targets: ${{ matrix.target }}
-                  workdir: util/dockerfiles
+                  workdir: ./dockerfiles-docker-build
+                  files: docker-bake.hcl
                   push: true

.github/workflows/gpu-tests.yaml

@@ -0,0 +1,96 @@
+---
+# This workflow runs all the Weekly GPU Tests.
+# For now this file is kept separate as we are still developing and testing
+# this workflow. It will eventually be merged with "weekly-tests.yaml"
+
+name: Weekly Tests (GPU)
+
+on:
+  # Runs every Sunday from 7AM UTC
+    schedule:
+        - cron: 00 7 * * 6
+  # Allows us to manually start workflow for testing
+    workflow_dispatch:
+
+jobs:
+    build-gem5:
+        runs-on: [self-hosted, linux, x64]
+        container: ghcr.io/gem5/gcn-gpu:latest
+        steps:
+            - uses: actions/checkout@v3
+              with:
+          # Scheduled workflows run on the default branch by default. We
+          # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+            - name: Build gem5
+              run: scons build/GCN3_X86/gem5.opt -j $(nproc) --ignore-style
+            - uses: actions/upload-artifact@v3
+              with:
+                  name: weekly-test-${{ github.run_number }}-attempt-${{ github.run_attempt }}-gem5-build-gcn3
+                  path: build/GCN3_X86/gem5.opt
+                  retention-days: 5
+            - run: echo "This job's status is ${{ job.status }}."
+
+    LULESH-tests:
+        runs-on: [self-hosted, linux, x64]
+        container: ghcr.io/gem5/gcn-gpu:latest
+        needs: build-gem5
+        timeout-minutes: 480 # 8 hours
+        steps:
+            - uses: actions/checkout@v3
+              with:
+                # Scheduled workflows run on the default branch by default. We
+                # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+
+            - name: Download build/GCN3_X86/gem5.opt
+              uses: actions/download-artifact@v3
+              with:
+                  name: weekly-test-${{ github.run_number }}-attempt-${{ github.run_attempt }}-gem5-build-gcn3
+                  path: build/GCN3_X86
+                # `download-artifact` does not preserve permissions so we need to set
+                # them again.
+            - run: chmod u+x build/GCN3_X86/gem5.opt
+
+            - name: Obtain LULESH
+              working-directory: ${{ github.workspace }}/lulesh
+              # Obtains the latest LULESH compatible with this version of gem5 via
+              # gem5 Resources.
+              run: build/GCN3_X86/gem5.opt util/obtain-resource.py lulesh -p lulesh
+
+            - name: Run LULUESH tests
+              working-directory: ${{ github.workspace }}
+              run: |
+                  build/GCN3_X86/gem5.opt configs/example/apu_se.py -n3 --mem-size=8GB --reg-alloc-policy=dynamic --benchmark-root="lulesh" -c \
+                  lulesh 0.01 2
+
+    HACC-tests:
+        runs-on: [self-hosted, linux, x64]
+        container: ghcr.io/gem5/gcn-gpu:latest
+        needs: build-gem5
+        timeout-minutes: 120 # 2 hours
+        steps:
+            - uses: actions/checkout@v3
+              with:
+          # Scheduled workflows run on the default branch by default. We
+          # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+            - uses: actions/download-artifact@v3
+              with:
+                  name: weekly-test-${{ github.run_number }}-attempt-${{ github.run_attempt }}-gem5-build-gcn3
+                  path: build/GCN3_X86
+            - run: chmod u+x build/GCN3_X86/gem5.opt
+            - name: make hip directory
+              run: mkdir hip
+            - name: Compile m5ops and x86
+              working-directory: ${{ github.workspace }}/util/m5
+              run: |
+                  export TERM=xterm-256color
+                  scons build/x86/out/m5
+            - name: Download tests
+              working-directory: ${{ github.workspace }}/hip
+              run: wget http://dist.gem5.org/dist/v22-1/test-progs/halo-finder/ForceTreeTest
+            - name: Run HACC tests
+              working-directory: ${{ github.workspace }}
+              run: |
+                  build/GCN3_X86/gem5.opt configs/example/apu_se.py -n3 --reg-alloc-policy=dynamic --benchmark-root=hip -c ForceTreeTest --options="0.5 0.1 64 0.1 1 N 12 rcb"

.github/workflows/scheduler.yaml

@@ -1,91 +0,0 @@
----
-name: Workflow Scheduler
-
-# GitHub scheduled workflows run on the default branch ('stable' in the case of
-# gem5). this means for changes in a workflow to take effect, the default
-# branch must be updated. This is not ideal as it requires regular commits into
-# the stable branch. Ideally we just want to update the workflow on develop and
-# have it run on the develop branch.
-#
-# This workflow is designed to run on the stable branch and will trigger other
-# workflows on the develop branch.
-#
-# To do so we simply schedule this workflow to run every hour and use some
-# simple bash logic to determine if the current time is when we want to run the
-# other workflows.
-
-on:
-    schedule:
-    # Runs every hour, 30 minutes past the hour.
-        - cron: 30 * * * *
-
-env:
-  # This is the token used to authenticate with GitHub.
-  # It is required to run the `gh` CLI.
-    GH_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-
-jobs:
-    schedule-workflows:
-        runs-on: ubuntu-latest
-        steps:
-            # This step is necessary to allow the `gh` CLI to be used in the
-            # following steps. The `gh` CLI is used to trigger the workflows.
-            # and needs to be used inside a the same repository where the
-            # workflows are defined.
-            - name: Checkout Repository
-              uses: actions/checkout@v4
-
-            - name: Record day and time
-              id: timedate-recorder
-              run: |
-                  # `date +H` returns the current hour as a number from
-                  # `00` to `23`.
-                  echo "HOUR=$(date +%H)" >> $GITHUB_OUTPUT
-
-                  # `date +%u` returns the day of the week as a number from
-                  # `1` to `7`.
-                  # `1` is Monday and `7` is Sunday.
-                  echo "DAY=$(date +%u)" >> $GITHUB_OUTPUT
-
-            - name: Daily Tests
-              env:
-                  HOUR: ${{ steps.timedate-recorder.outputs.HOUR }}
-              run: |
-                  # If current time is 7pm then run the workflow.
-                  if [[ $HOUR  == '19' ]]
-                  then
-                    gh workflow run daily-tests.yaml --ref develop >/dev/null
-                    echo "Daily test scheduled to run on develop branch."
-                  else
-                    echo "Daily tests not scheduled."
-                  fi
-
-            - name: Weekly Tests
-              env:
-                  DAY: ${{ steps.timedate-recorder.outputs.DAY }}
-                  HOUR: ${{ steps.timedate-recorder.outputs.HOUR }}
-              run: |
-                  # If the current day is Friday and the time is 7pm then run
-                  # the workflow.
-                  if [[ $DAY == '5' ]] && [[ $HOUR  == '19' ]]
-                  then
-                    gh workflow run weekly-tests.yaml --ref develop >/dev/null
-                    echo "Weekly test scheduled to run on develop branch."
-                  else
-                    echo "Weekly tests not scheduled."
-                  fi
-
-            - name: Compiler Tests
-              env:
-                  DAY: ${{ steps.timedate-recorder.outputs.DAY }}
-                  HOUR: ${{ steps.timedate-recorder.outputs.HOUR }}
-              run: |
-                  # If the current day is Tuesday and the time is 9pm then run
-                  # the workflow.
-                  if [[ $DAY == '2' ]] && [[ $HOUR  == '21' ]]
-                  then
-                    gh workflow run compiler-tests.yaml --ref develop >/dev/null
-                    echo "Compiler tests scheduled to run on the develop branch."
-                  else
-                    echo "Compiler tests not scheduled."
-                  fi

.github/workflows/weekly-tests.yaml

@@ -4,255 +4,98 @@
 name: Weekly Tests
 
 on:
-    # This is triggered weekly via the 'scheduler.yaml' workflow.
+  # Runs every Sunday from 7AM UTC
+    schedule:
+        - cron: 00 7 * * 6
+  # Allows us to manually start workflow for testing
     workflow_dispatch:
 
 jobs:
-
-    get-date:
-        runs-on: ubuntu-latest
+    build-gem5:
+        runs-on: [self-hosted, linux, x64]
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
         outputs:
-            date: ${{ steps.date.outputs.date }}
+            build-name: ${{ steps.artifact-name.outputs.name }}
         steps:
-            - name: Get the current date
-              id: date
-              run: echo "date=$(date +'%Y-%m-%d')" >> $GITHUB_ENV
+            - uses: actions/checkout@v3
+              with:
+          # Scheduled workflows run on the default branch by default. We
+          # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+            - id: artifact-name
+              run: echo "name=$(date +"%Y-%m-%d_%H.%M.%S")-ALL" >> $GITHUB_OUTPUT
+            - name: Build gem5
+              run: |
+                  scons build/ALL/gem5.opt -j $(nproc)
+            - uses: actions/upload-artifact@v3
+              with:
+                  name: ${{ steps.artifact-name.outputs.name }}
+                  path: build/ALL/gem5.opt
+                  retention-days: 5
+            - run: echo "This job's status is ${{ job.status }}."
 
-    # start running the very-long tests
+  # start running the very-long tests
     testlib-very-long-tests:
         strategy:
             fail-fast: false
             matrix:
-                test-type: [gem5_library_example_tests, gem5_resources, stdlib, parsec_benchmarks, x86_boot_tests]
+                test-type: [gem5_library_example_tests, gem5_resources, parsec_benchmarks, x86_boot_tests]
         runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
+        needs: [build-gem5]
         timeout-minutes: 4320 # 3 days
-        needs: get-date
         steps:
             - name: Clean runner
               run: rm -rf ./* || true rm -rf ./.??* || true rm -rf ~/.cache || true
-            - uses: actions/checkout@v4
-
-            - name: Cache build/ALL
-              uses: actions/cache@v4
+            - uses: actions/checkout@v3
               with:
+        # Scheduled workflows run on the default branch by default. We
+        # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+            - uses: actions/download-artifact@v3
+              with:
+                  name: ${{needs.build-gem5.outputs.build-name}}
                   path: build/ALL
-                  key: testlib-build-all-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-all
-
+            - run: chmod u+x build/ALL/gem5.opt
             - name: very-long ${{ matrix.test-type }}
               working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run gem5/${{ matrix.test-type }} --length very-long -j$(nproc) -vv
-            - name: upload results
+              run: ./main.py run gem5/${{ matrix.test-type }} --length very-long --skip-build -vv -t $(nproc)
+            - name: create zip of results
               if: success() || failure()
-              uses: actions/upload-artifact@v4
+              run: |
+                  apt-get -y install zip
+                  zip -r output.zip tests/testing-results
+            - name: upload zip
+              if: success() || failure()
+              uses: actions/upload-artifact@v3
               env:
                   MY_STEP_VAR: ${{ matrix.test-type }}_COMMIT.${{github.sha}}_RUN.${{github.run_id}}_ATTEMPT.${{github.run_attempt}}
               with:
                   name: ${{ env.MY_STEP_VAR }}
-                  path: tests/testing-results
+                  path: output.zip
                   retention-days: 7
             - run: echo "This job's status is ${{ job.status }}."
 
-    # The GPU tests are run in different jobs beacuse they take a long time to run. This way we can run them in parallel on different runners.
-    gpu-test-hacc:
-        runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/gcn-gpu:latest
-        timeout-minutes: 720 # 12 hours
-        needs: get-date
-
-        steps:
-            - uses: actions/checkout@v4
-              with:
-                  ref: develop
-
-            - name: Cache build/VEGA_X86
-              uses: actions/cache@v4
-              with:
-                  path: build/VEGA_X86
-                  key: testlib-build-vega-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-vega
-
-            - name: Run Testlib GPU Tests
-              working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run --length=very-long -vvv -j $(nproc) --host gcn_gpu --uid SuiteUID:tests/gem5/gpu/test_gpu_apu_se.py:gpu-apu-se-hacc-VEGA_X86-gcn_gpu-opt
-
-            - name: Upload results
-              if: success() || failure()
-              uses: actions/upload-artifact@v4.0.0
-              with:
-                  name: gpu_tests_hacc_${{github.sha}}_RUN_${{github.run_id}}_ATTEMPT_${{github.run_attempt}}
-                  path: tests/testing-results
-                  retention-days: 7
-
-    gpu-test-lulesh:
-        runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/gcn-gpu:latest
-        timeout-minutes: 720 # 12 hours
-        needs: get-date
-
-        steps:
-            - uses: actions/checkout@v4
-              with:
-                  ref: develop
-
-            - name: Cache build/VEGA_X86
-              uses: actions/cache@v4
-              with:
-                  path: build/VEGA_X86
-                  key: testlib-build-vega-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-vega
-
-            - name: Run Testlib GPU Tests
-              working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run --length=very-long -vvv -j $(nproc) --host gcn_gpu --uid SuiteUID:tests/gem5/gpu/test_gpu_apu_se.py:gpu-apu-se-lulesh-VEGA_X86-gcn_gpu-opt
-
-            - name: Upload results
-              if: success() || failure()
-              uses: actions/upload-artifact@v4.0.0
-              with:
-                  name: gpu_tests_lulesh_${{github.sha}}_RUN_${{github.run_id}}_ATTEMPT_${{github.run_attempt}}
-                  path: tests/testing-results
-                  retention-days: 7
-
-    gpu-test-pannotia-bc:
-        runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/gcn-gpu:latest
-        timeout-minutes: 720 # 12 hours
-        needs: get-date
-
-        steps:
-            - uses: actions/checkout@v4
-              with:
-                  ref: develop
-
-            - name: Cache build/VEGA_X86
-              uses: actions/cache@v4
-              with:
-                  path: build/VEGA_X86
-                  key: testlib-build-vega-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-vega
-
-            - name: Run Testlib GPU Tests
-              working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run --length=very-long -vvv -j $(nproc) --host gcn_gpu --uid SuiteUID:tests/gem5/gpu/test_gpu_pannotia.py:gpu-apu-se-pannotia-bc-1k-128k-VEGA_X86-gcn_gpu-opt
-
-            - name: Upload results
-              if: success() || failure()
-              uses: actions/upload-artifact@v4.0.0
-              with:
-                  name: gpu_tests_pannotia_bc_${{github.sha}}_RUN_${{github.run_id}}_ATTEMPT_${{github.run_attempt}}
-                  path: tests/testing-results
-                  retention-days: 7
-
-    gpu-test-pannotia-color-maxmin:
-        runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/gcn-gpu:latest
-        timeout-minutes: 720 # 12 hours
-        needs: get-date
-
-        steps:
-            - uses: actions/checkout@v4
-              with:
-                  ref: develop
-
-            - name: Cache build/VEGA_X86
-              uses: actions/cache@v4
-              with:
-                  path: build/VEGA_X86
-                  key: testlib-build-vega-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-vega
-
-            - name: Run Testlib GPU Tests
-              working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run --length=very-long -vvv -j $(nproc) --host gcn_gpu --uid SuiteUID:tests/gem5/gpu/test_gpu_pannotia.py:gpu-apu-se-pannotia-color-maxmin-1k-128k-VEGA_X86-gcn_gpu-opt
-
-            - name: Upload results
-              if: success() || failure()
-              uses: actions/upload-artifact@v4.0.0
-              with:
-                  name: gpu_tests_pannotia_color_maxmin_${{github.sha}}_RUN_${{github.run_id}}_ATTEMPT_${{github.run_attempt}}
-                  path: tests/testing-results
-                  retention-days: 7
-
-    gpu-test-pannotia-color-max:
-        runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/gcn-gpu:latest
-        timeout-minutes: 720 # 12 hours
-        needs: get-date
-
-        steps:
-            - uses: actions/checkout@v4
-              with:
-                  ref: develop
-
-            - name: Cache build/VEGA_X86
-              uses: actions/cache@v4
-              with:
-                  path: build/VEGA_X86
-                  key: testlib-build-vega-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-vega
-
-            - name: Run Testlib GPU Tests
-              working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run --length=very-long -vvv -j $(nproc) --host gcn_gpu --uid SuiteUID:tests/gem5/gpu/test_gpu_pannotia.py:gpu-apu-se-pannotia-color-max-1k-128k-VEGA_X86-gcn_gpu-opt
-
-            - name: Upload results
-              if: success() || failure()
-              uses: actions/upload-artifact@v4.0.0
-              with:
-                  name: gpu_tests_pannotia_color_max_${{github.sha}}_RUN_${{github.run_id}}_ATTEMPT_${{github.run_attempt}}
-                  path: tests/testing-results
-                  retention-days: 7
-
-    gpu-test-pannotia-fw-hip:
-        runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/gcn-gpu:latest
-        timeout-minutes: 2160 # 36 hours
-        needs: get-date
-
-        steps:
-            - uses: actions/checkout@v4
-              with:
-                  ref: develop
-
-            - name: Cache build/VEGA_X86
-              uses: actions/cache@v4
-              with:
-                  path: build/VEGA_X86
-                  key: testlib-build-vega-${{ needs.get-date.outputs.date }}
-                  restore-keys: |
-                      testlib-build-vega
-
-            - name: Run Testlib GPU Tests
-              working-directory: ${{ github.workspace }}/tests
-              run: ./main.py run --length=very-long -vvv -j $(nproc) --host gcn_gpu --uid SuiteUID:tests/gem5/gpu/test_gpu_pannotia.py:gpu-apu-se-pannotia-fw-hip-1k-128k-VEGA_X86-gcn_gpu-opt
-
-            - name: Upload results
-              if: success() || failure()
-              uses: actions/upload-artifact@v4.0.0
-              with:
-                  name: gpu_tests_pannotia_fw_hip_${{github.sha}}_RUN_${{github.run_id}}_ATTEMPT_${{github.run_attempt}}
-                  path: tests/testing-results
-                  retention-days: 7
-
     dramsys-tests:
         runs-on: [self-hosted, linux, x64]
-        container: ghcr.io/gem5/ubuntu-24.04_all-dependencies:latest
+        container: ghcr.io/gem5/ubuntu-22.04_all-dependencies:latest
         timeout-minutes: 4320 # 3 days
         steps:
-            - uses: actions/checkout@v4
+            - uses: actions/checkout@v3
+              with:
+          # Scheduled workflows run on the default branch by default. We
+          # therefore need to explicitly checkout the develop branch.
+                  ref: develop
+
             - name: Checkout DRAMSys
               working-directory: ${{ github.workspace }}/ext/dramsys
-              run: git clone https://github.com/tukl-msd/DRAMSys --branch v5.1 --depth 1 DRAMSys
+              run: |
+                  git clone https://github.com/tukl-msd/DRAMSys DRAMSys
+                  cd DRAMSys
+                  git checkout -b gem5 09f6dcbb91351e6ee7cadfc7bc8b29d97625db8f
+                  git submodule update --init --recursive
 
-              # gem5 is built separately because it depends on the DRAMSys library
+      # gem5 is built separately because it depends on the DRAMSys library
             - name: Build gem5
               working-directory: ${{ github.workspace }}
               run: scons build/ALL/gem5.opt -j $(nproc)
@@ -269,15 +112,9 @@ jobs:
         # I.e., if we want to stop pull requests from being merged if the
         # weekly tests are failing we can add this job as a required status
         # check.
-        runs-on: ubuntu-latest
+        runs-on: ubuntu-22.04
         needs:
             - testlib-very-long-tests
             - dramsys-tests
-            - gpu-test-hacc
-            - gpu-test-lulesh
-            - gpu-test-pannotia-bc
-            - gpu-test-pannotia-color-maxmin
-            - gpu-test-pannotia-color-max
-            - gpu-test-pannotia-fw-hip
         steps:
             - run: echo "This weekly tests have passed."

.gitignore

@@ -1,5 +1,4 @@
 build
-gem5_build
 parser.out
 parsetab.py
 cscope.files
@@ -10,7 +9,6 @@ cscope.out
 .*.swo
 m5out
 /src/doxygen/html
-/docs/_build
 /ext/dramsim2/DRAMSim2
 /ext/mcpat/regression/*/*.out
 /util/m5/*.o
@@ -34,5 +32,3 @@ configs/example/memcheck.cfg
 configs/dram/lowp_sweep.cfg
 .pyenv
 .vscode
-typings
-.DS_Store

.mailmap

@@ -1,11 +1,8 @@
 Abdul Mutaal Ahmad <abdul.mutaal@gmail.com>
 adarshpatil <adarshpatil123@gmail.com>
-Aditya K Kamath <a_kamath@hotmail.com> aditya <a_kamath@hotmail.com>
 Adrià Armejach <adria.armejach@bsc.es> Adrià Armejach <adria.armejach@gmail.com>
-Adrià Armejach <adria.armejach@bsc.es> Adrià Armejach <66964292+aarmejach@users.noreply.github.com>
 Adrian Herrera <adrian.herrera@arm.com>
 Adrien Pesle <adrien.pesle@arm.com>
-Adwaith R Krishna <adwaithrk19@gmail.com>
 Akash Bagdia <akash.bagdia@ARM.com> Akash Bagdia <akash.bagdia@arm.com>
 Alec Roelke <alec.roelke@gmail.com> Alec Roelke <ar4jc@virginia.edu>
 Alexander Klimov <Alexander.Klimov@arm.com>
@@ -13,19 +10,21 @@ Alexandru Dutu <alexandru.dutu@amd.com> Alexandru <alexandru.dutu@amd.com>
 Alex Richardson <alexrichardson@google.com>
 Ali Jafri <ali.jafri@arm.com>
 Ali Saidi <Ali.Saidi@arm.com> Ali Saidi <ali.saidi@arm.com>
+Ali Saidi <Ali.Saidi@arm.com> Ali Saidi <Ali.Saidi@ARM.com>
 Ali Saidi <Ali.Saidi@arm.com> Ali Saidi <saidi@eecs.umich.edu>
 Alistair Delva <adelva@google.com>
-Alvaro Moreno <alvaro.moreno@bsc.es>
 Amin Farmahini <aminfar@gmail.com>
 Anders Handler <s052838@student.dtu.dk>
 Andrea Mondelli <andrea.mondelli@huawei.com> Andrea Mondelli <andrea.mondelli@ucf.edu>
+Andrea Mondelli <andrea.mondelli@huawei.com> Andrea Mondelli <Andrea.Mondelli@ucf.edu>
 Andrea Pellegrini <andrea.pellegrini@gmail.com>
 Andreas Hansson <andreas.hanson@arm.com> Andreas Hansson <andreas.hansson>
 Andreas Hansson <andreas.hanson@arm.com> Andreas Hansson <andreas.hansson@arm.com>
+Andreas Hansson <andreas.hanson@arm.com> Andreas Hansson <Andreas.Hansson@ARM.com>
 Andreas Hansson <andreas.hanson@arm.com> Andreas Hansson <andreas.hansson@armm.com>
 Andreas Sandberg <Andreas.Sandberg@arm.com> Andreas Sandberg <andreas.sandberg@arm.com>
+Andreas Sandberg <Andreas.Sandberg@arm.com> Andreas Sandberg <Andreas.Sandberg@ARM.com>
 Andreas Sandberg <Andreas.Sandberg@arm.com> Andreas Sandberg <andreas@sandberg.pp.se>
-Andreas Sandberg <Andreas.Sandberg@arm.com> Andreas Sandberg <andreas@sandberg.uk>
 Andrew Bardsley <Andrew.Bardsley@arm.com> Andrew Bardsley <Andreas.Bardsley@arm.com>
 Andrew Lukefahr <lukefahr@umich.edu>
 Andrew Schultz <alschult@umich.edu>
@@ -33,14 +32,11 @@ Andriani Mappoura <andriani.mappoura@arm.com>
 Angie Lee <peiyinglee@google.com>
 Anis Peysieux <anis.peysieux@inria.fr>
 Ani Udipi <ani.udipi@arm.com>
-anoop <mysanoop@gmail.com>
 Anouk Van Laer <anouk.vanlaer@arm.com>
 ARM gem5 Developers <none@none>
 Arthur Perais <Arthur.Perais@univ-grenoble-alpes.fr> Arthur Perais <arthur.perais@inria.fr>
 Arun Rodrigues <afrodri@gmail.com>
 Ashkan Tousi <ashkan.tousimojarad@arm.com>
-atrah22 <atul.rahman@outlook.com>
-Atri Bhattacharyya <atri.bhattacharyya@epfl.ch>
 Austin Harris <austinharris@utexas.edu> Austin Harris <mail@austin-harris.com>
 Avishai Tvila <avishai.tvila@gmail.com>
 Ayaz Akram <yazakram@ucdavis.edu>
@@ -52,7 +48,6 @@ Bjoern A. Zeeb <baz21@cam.ac.uk>
 Blake Hechtman <bah13@duke.edu> Blake Hechtman <blake.hechtman@amd.com>
 Blake Hechtman <bah13@duke.edu> Blake Hechtman ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <bah13@duke.edu>
 Bobby R. Bruce <bbruce@ucdavis.edu> Bobby Bruce <bbruce@amarillo.cs.ucdavis.edu>
-Bobby R. Bruce <bbruce@ucdavis.edu> Bobby Bruce <bbruce@ucdavis.edu>
 Boris Shingarov <shingarov@gmail.com> Boris Shingarov <shingarov@labware.com>
 Brad Beckmann <brad.beckmann@amd.com> Brad Beckmann <Brad.Beckmann@amd.com>
 Brad Beckmann <brad.beckmann@amd.com> Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <Brad.Beckmann@amd.com>
@@ -65,13 +60,15 @@ Brian Grayson <b.grayson@samsung.com>
 Cagdas Dirik <cdirik@micron.com> cdirik <cdirik@micron.com>
 Carlos Falquez <c.falquez@fz-juelich.de>
 Chander Sudanthi <chander.sudanthi@arm.com> Chander Sudanthi <Chander.Sudanthi@arm.com>
+Chander Sudanthi <chander.sudanthi@arm.com> Chander Sudanthi <Chander.Sudanthi@ARM.com>
 Charles Jamieson <cjamieson2@wisc.edu>
-Chen Meng <tundriolaxy@gmail.com>
+CHEN Meng <tundriolaxy@gmail.com>
 Chen Zou <chenzou@uchicago.edu>
 Chia-You Chen <hortune@google.com>
-Marcus Chow <marcus.chow@amd.com>
+Chow, Marcus <marcus.chow@amd.com>
 Chris Adeniyi-Jones <Chris.Adeniyi-Jones@arm.com>
 Chris Emmons <chris.emmons@arm.com> Chris Emmons <Chris.Emmons@arm.com>
+Chris Emmons <chris.emmons@arm.com> Chris Emmons <Chris.Emmons@ARM.com>
 Chris January <chris.january@arm.com>
 Christian Menard <christian.menard@tu-dresden.de> Christian Menard <Christian.Menard@tu-dresden.de>
 Christopher Torng <clt67@cornell.edu>
@@ -86,19 +83,17 @@ Daecheol You <daecheol.you@samsung.com>
 Dam Sunwoo <dam.sunwoo@arm.com>
 Dan Gibson <gibson@cs.wisc.edu>
 Daniel Carvalho <odanrc@yahoo.com.br> Daniel <odanrc@yahoo.com.br>
-Daniel Carvalho <odanrc@yahoo.com.br> Daniel Carvalho <odanrc@users.noreply.github.com>
 Daniel Carvalho <odanrc@yahoo.com.br> Daniel R. Carvalho <odanrc@yahoo.com.br>
 Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
 Daniel Johnson <daniel.johnson@arm.com>
-Daniel Kouchekinia <DanKouch@users.noreply.github.com>
 Daniel Sanchez <sanchezd@stanford.edu>
 Davide Basilio Bartolini <davide.basilio.bartolini@huawei.com>
 David Guillen-Fandos <david.guillen@arm.com> David Guillen <david.guillen@arm.com>
 David Guillen-Fandos <david.guillen@arm.com> David Guillen Fandos <david.guillen@arm.com>
 David Hashe <david.hashe@amd.com> David Hashe <david.j.hashe@gmail.com>
 David Oehmke <doehmke@umich.edu>
-David Schall <david.schall@ed.ac.uk> David Schall <david.schall2@arm.com>
-Derek Christ <dchrist@rhrk.uni-kl.de> Derek Christ <44267643+derchr@users.noreply.github.com>
+David Schall <david.schall2@arm.com>
+Derek Christ <dchrist@rhrk.uni-kl.de>
 Derek Hower <drh5@cs.wisc.edu>
 Deyaun Guo <guodeyuan@tsinghua.org.cn> Deyuan Guo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <guodeyuan@tsinghua.org.cn>
 Deyaun Guo <guodeyuan@tsinghua.org.cn> Deyuan Guo <guodeyuan@tsinghua.org.cn>
@@ -112,12 +107,11 @@ Earl Ou <shunhsingou@google.com>
 eavivi <eavivi@ucdavis.edu>
 Éder F. Zulian <zulian@eit.uni-kl.de>
 Edmund Grimley Evans <Edmund.Grimley-Evans@arm.com>
-Eduardo José Gómez Hernández <eduardojose.gomez@um.es> Eduardo José Gómez Hernández <git@edujgh.net>
+Eduardo José Gómez Hernández <eduardojose.gomez@um.es>
 Eliot Moss <moss@cs.umass.edu>
 Emilio Castillo <castilloe@unican.es> Emilio Castillo <ecastill@bsc.es>
 Emilio Castillo <castilloe@unican.es> Emilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <castilloe@unican.es>
 Emily Brickey <esbrickey@ucdavis.edu>
-Emin Gadzhiev <e.gadzhiev.mhk@gmail.com>
 Erfan Azarkhish <erfan.azarkhish@unibo.it>
 Erhu <fengerhu.ipads@gmail.com>
 Eric Van Hensbergen <eric.vanhensbergen@arm.com> Eric Van Hensbergen <Eric.VanHensbergen@ARM.com>
@@ -131,12 +125,11 @@ Gabe Black <gabe.black@gmail.com> Gabe Black <gabeblack@google.com>
 Gabe Black <gabe.black@gmail.com> Gabe Black <gblack@eecs.umich.edu>
 Gabe Loh <gabriel.loh@amd.com> gloh <none@none>
 Gabor Dozsa <gabor.dozsa@arm.com>
-Gabriel Busnot <gabriel.busnot@arteris.com> Gabriel Busnot <gabriel.busnot@cea.fr>
-Gabriel Busnot <gabriel.busnot@arteris.com> Gabriel Busnot <gabibusnot@gmail.com>
+Gabriel Busnot <gabriel.busnot@arteris.com>
 gauravjain14 <gjain6@wisc.edu>
-Gautham Pathak <gspathak@gitlab.uwaterloo.ca>
 Gedare Bloom <gedare@rtems.org> Gedare Bloom <gedare@gwmail.gwu.edu>
 Gene Wu <gene.wu@arm.com> Gene WU <gene.wu@arm.com>
+Gene WU <gene.wu@arm.com> Gene Wu <Gene.Wu@arm.com>
 Geoffrey Blake <geoffrey.blake@arm.com> Geoffrey Blake <blakeg@umich.edu>
 Geoffrey Blake <geoffrey.blake@arm.com> Geoffrey Blake <Geoffrey.Blake@arm.com>
 Georg Kotheimer <georg.kotheimer@mailbox.tu-dresden.de>
@@ -147,14 +140,10 @@ GWDx <gwdx@mail.ustc.edu.cn>
 Hamid Reza Khaleghzadeh <khaleghzadeh@gmail.com> Hamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <khaleghzadeh@gmail.com>
 handsomeliu <handsomeliu@google.com>
 Hanhwi Jang <jang.hanhwi@gmail.com>
-Harshil Patel <hpppatel@ucdavis.edu> Harshil Patel <harshilp2107@gmail.com>
-Harshil Patel <hpppatel@ucdavis.edu> Harshil Patel <91860903+Harshil2107@users.noreply.github.com>
-Wenjian He <wheac@connect.ust.hk>
-HJikram <humzajahangirikram@gmail.com>
-Hoa Nguyen <hn@hnpl.org> Hoa Nguyen <hoanguyen@ucdavis.edu>
+Hoa Nguyen <hoanguyen@ucdavis.edu>
 Hongil Yoon <ongal@cs.wisc.edu>
 Hsuan Hsu <hsuan.hsu@mediatek.com>
-hungweihsu <hungweihsu@google.com> hungweihsuG <145444687+hungweihsuG@users.noreply.github.com>
+huangjs <jiasen.hjs@alibaba-inc.com>
 Hussein Elnawawy <hussein.elnawawy@gmail.com>
 Ian Jiang <ianjiang.ict@gmail.com>
 IanJiangICT <ianjiang.ict@gmail.com>
@@ -163,13 +152,9 @@ Iru Cai <mytbk920423@gmail.com>
 Isaac Richter <isaac.richter@rochester.edu>
 Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
 Ivan Pizarro <ivan.pizarro@metempsy.com>
-Ivan Turasov <turasov.ivan@gmail.com>
-Ivana Mitrovic <imitrovic@ucdavis.edu> Ivana Mitrovic <ivanamit91@gmail.com>
-Ivana Mitrovic <imitrovic@ucdavis.edu> ivanaamit <ivanamit91@gmail.com>
-Jack Whitham <jack-m5ml2@cs.york.ac.uk>
+Jack Whitham <jack-m5ml2@cs.york.ac.uk> Jack Whitman <jack-m5ml2@cs.york.ac.uk>
 Jairo Balart <jairo.balart@metempsy.com>
 Jakub Jermar <jakub@jermar.eu>
-James Braun <jebraun3@wisc.edu>
 James Clarkson <james.clarkson@arm.com>
 Jan-Peter Larsson <jan-peter.larsson@arm.com>
 Jan Vrany <jan.vrany@labware.com>
@@ -189,8 +174,8 @@ Jayneel Gandhi <jayneel@cs.wisc.edu>
 Jennifer Treichler <jtreichl@umich.edu>
 Jerin Joy <joy@rivosinc.com>
 Jiajie Chen <c@jia.je>
-Jiasen Huang <jiasen.hjs@alibaba-inc.com> Jiasen <jiasen.hjs@alibaba-inc.com>
-Jiasen Huang <jiasen.hjs@alibaba-inc.com> huangjs <jiasen.hjs@alibaba-inc.com>
+Jiasen Huang <jiasen.hjs@alibaba-inc.com>
+Jiasen <jiasen.hjs@alibaba-inc.com>
 Jiayi Huang <jyhuang91@gmail.com>
 jiegec <noc@jiegec.ac.cn>
 Jieming Yin <jieming.yin@amd.com> jiemingyin <bjm419@gmail.com>
@@ -203,17 +188,14 @@ Joel Hestness <jthestness@gmail.com> Joel Hestness <hestness@cs.wisc.edu>
 Joël Porquet-Lupine <joel@porquet.org>
 John Alsop <johnathan.alsop@amd.com>
 John Kalamatianos <john.kalamatianos@amd.com> jkalamat <john.kalamatianos@amd.com>
-Johnny <johnnyko@google.com>
 Jordi Vaquero <jordi.vaquero@metempsy.com>
 Jose Marinho <jose.marinho@arm.com>
 Juan M. Cebrian <jm.cebriangonzalez@gmail.com>
 Jui-min Lee <fcrh@google.com>
-Kai Ren <kai.ren@streamcomputing.com> kai.ren <kai.ren@streamcomputing.com>
-Kai Ren <kai.ren@streamcomputing.com> Kai Ren <binarystar2006@outlook.com>
-KaiBatley <68886332+KaiBatley@users.noreply.github.com>
+kai.ren <kai.ren@streamcomputing.com> Kai Ren <binarystar2006@outlook.com>
 Kanishk Sugand <kanishk.sugand@arm.com>
 Karthik Sangaiah <karthik.sangaiah@arm.com>
-Kaustav Goswami <kggoswami@ucdavis.edu> Kaustav Goswami <39310478+kaustav-goswami@users.noreply.github.com>
+Kaustav Goswami <kggoswami@ucdavis.edu>
 Kelly Nguyen <klynguyen@ucdavis.edu>
 Ke Meng <mengke97@hotmail.com>
 Kevin Brodsky <kevin.brodsky@arm.com>
@@ -224,16 +206,11 @@ Koan-Sin Tan <koansin.tan@gmail.com>
 Korey Sewell <ksewell@umich.edu>
 Krishnendra Nathella <Krishnendra.Nathella@arm.com> Krishnendra Nathella <krinat01@arm.com>
 ksco <numbksco@gmail.com>
-Kunal Pai <kunpai@ucdavis.edu> Kunal Pai <62979320+kunpai@users.noreply.github.com>
-Kunal Pai <kunpai@ucdavis.edu> kunpai <kunpai@ucdavis.edu>
-Kunal Pai <kunpai@ucdavis.edu> paikunal <kunpai@ucdavis.edu>
-Kunal Pai <kunpai@ucdavis.edu> KUNAL PAI <kunpai@ucdavis.edu>
+kunpai <kunpai@ucdavis.edu>
 Kyle Roarty <kyleroarty1716@gmail.com> Kyle Roarty <Kyle.Roarty@amd.com>
 Laura Hinman <llhinman@ucdavis.edu>
 Lena Olson <leolson@google.com> Lena Olson <lena@cs.wisc,edu>
 Lena Olson <leolson@google.com> Lena Olson <lena@cs.wisc.edu>
-Leo Redivo <lredivo@ucdavis.edu> leoredivo <94771718+leoredivo@users.noreply.github.com>
-Lingkang <karlzhu12@gmail.com>
 Lisa Hsu <Lisa.Hsu@amd.com> Lisa Hsu <hsul@eecs.umich.edu>
 Lluc Alvarez <lluc.alvarez@bsc.es>
 Lluís Vilanova <vilanova@ac.upc.edu> Lluis Vilanova <vilanova@ac.upc.edu>
@@ -244,11 +221,9 @@ Mahyar Samani <msamani@ucdavis.edu>
 Majid Jalili <majid0jalili@gmail.com>
 Malek Musleh <malek.musleh@gmail.com> Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E) <nilay@cs.wisc.edu>
 Marc Mari Barcelo <marc.maribarcelo@arm.com>
-Marc Orr <marc.orr@gmail.com> Marc Orr <morr@cs.wisc.edu>
 Marco Balboni <Marco.Balboni@ARM.com>
-Marco Chen <mc@soc.pub>
 Marco Elver <Marco.Elver@ARM.com> Marco Elver <marco.elver@ed.ac.uk>
-Marco Kurzynski <marcokurzynski@icloud.com>
+Marc Orr <marc.orr@gmail.com> Marc Orr <morr@cs.wisc.edu>
 Marjan Fariborz <mfariborz@ucdavis.edu> marjanfariborz <mfariborz@ucdavis.edu>
 Mark Hildebrand <mhildebrand@ucdavis.edu>
 Marton Erdos <marton.erdos@arm.com>
@@ -258,18 +233,20 @@ Matteo Andreozzi <matteo.andreozzi@arm.com> Matteo Andreozzi <Matteo.Andreozzi@a
 Matteo M. Fusi <matteo.fusi@bsc.es>
 Matt Evans <matt.evans@arm.com> Matt Evans <Matt.Evans@arm.com>
 Matthew Poremba <matthew.poremba@amd.com> Matthew Poremba <Matthew.Poremba@amd.com>
-Matthias Boettcher <matthias.boettcher@arm.com>
 Matthias Hille <matthiashille8@gmail.com>
-Matthias Jung <matthias.jung@iese.fraunhofer.de> Matthias Jung <jungma@eit.uni-kl.de>
+Matthias Jung <jungma@eit.uni-kl.de>
+Matthias Jung <matthias.jung@iese.fraunhofer.de>
+Matt Horsnell <matt.horsnell@arm.com> Matt Horsnell <matt.horsnell@ARM.com>
 Matt Horsnell <matt.horsnell@arm.com> Matt Horsnell <Matt.Horsnell@arm.com>
+Matt Horsnell <matt.horsnell@arm.com>Matt Horsnell <Matt.Horsnell@ARM.com>
 Matt Poremba <matthew.poremba@amd.com> Matt Poremba <Matthew.Poremba@amd.com>
-Matt Sinclair <mattdsinclair.wisc@gmail.com> Matt Sinclair <mattdsinclair@gmail.com>
-Matt Sinclair <mattdsinclair.wisc@gmail.com> Matthew Sinclair <matthew.sinclair@amd.com>
+Matt Sinclair <mattdsinclair@gmail.com> Matthew Sinclair <matthew.sinclair@amd.com>
+Matt Sinclair <mattdsinclair.wisc@gmail.com> Matt Sinclair <Matthew.Sinclair@amd.com>
 Maurice Becker <madnaurice@googlemail.com>
 Maxime Martinasso <maxime.cscs@gmail.com>
 Maximilian Stein <maximilian.stein@tu-dresden.de>Maximilian Stein <m@steiny.biz>
 Maximilien Breughe <maximilien.breughe@elis.ugent.be> Maximilien Breughe <Maximilien.Breughe@elis.ugent.be>
-Melissa Jost <melissakjost@gmail.com> Melissa Jost <50555529+mkjost0@users.noreply.github.com>
+Melissa Jost <melissakjost@gmail.com>
 Michael Adler <Michael.Adler@intel.com>
 Michael Boyer <Michael.Boyer@amd.com>
 Michael LeBeane <michael.lebeane@amd.com> Michael LeBeane <Michael.Lebeane@amd.com>
@@ -285,6 +262,7 @@ Min Kyu Jeong <minkyu.jeong@arm.com> Min Kyu Jeong <MinKyu.Jeong@arm.com>
 Mitch Hayenga <mitch.hayenga@arm.com> Mitchell Hayenga <Mitchell.Hayenga@ARM.com>
 Mitch Hayenga <mitch.hayenga@arm.com> Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E) <mitch.hayenga+gem5@gmail.com>
 Mitch Hayenga <mitch.hayenga@arm.com> Mitch Hayenga <Mitch.Hayenga@arm.com>
+Mitch Hayenga <mitch.hayenga@arm.com> Mitch Hayenga <Mitch.Hayenga@ARM.com>
 Mitch Hayenga <mitch.hayenga@arm.com> Mitch Hayenga <mitch.hayenga+gem5@gmail.com>
 Mohammad Alian <m.alian1369@gmail.com>
 Monir Mozumder <monir.mozumder@amd.com>
@@ -301,17 +279,13 @@ Nathan Binkert <nate@binkert.org> Nathan Binkert <binkertn@umich.edu>
 Nayan Deshmukh <nayan26deshmukh@gmail.com>
 Neha Agarwal <neha.agarwal@arm.com>
 Neil Natekar <nanatekar@ucdavis.edu>
-Nicholas Lindsay <nicholas.lindsay@arm.com> Nicholas Lindsay <Nicholas.Lindsey@arm.com>
-Nicholas Mosier <nmosier@stanford.edu> Nicholas Mosier <nh.mosier@gmail.com>
+Nicholas Lindsay <nicholas.lindsay@arm.com>
 Nicolas Boichat <drinkcat@google.com>
 Nicolas Derumigny <nderumigny@gmail.com>
 Nicolas Zea <nicolas.zea@gmail.com>
-Nikolaos Kyparissas <nikolaos.kyparissas@arm.com>
 Nikos Nikoleris <nikos.nikoleris@arm.com> Nikos Nikoleris <nikos.nikoleris@gmail.com>
 Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E) <nilay@cs.wisc.edu>
 Nils Asmussen <nils.asmussen@barkhauseninstitut.org> Nils Asmussen <nilsasmussen7@gmail.com>
-Nitesh Narayana <nitesh.dps@gmail.com>
-Nitish Arya <42148385+aryanitish@users.noreply.github.com>
 Noah Katz <nkatz@rivosinc.com>
 ntampouratzis <ntampouratzis@isc.tuc.gr>
 Nuwan Jayasena <Nuwan.Jayasena@amd.com>
@@ -319,6 +293,7 @@ Ola Jeppsson <ola.jeppsson@gmail.com>
 Omar Naji <Omar.Naji@arm.com>
 Onur Kayiran <onur.kayiran@amd.com>
 Pablo Prieto <pablo.prieto@unican.es>
+paikunal <kunpai@ucdavis.edu>
 Palle Lyckegaard <palle@lyckegaard.dk>
 Pau Cabre <pau.cabre@metempsy.com>
 Paul Rosenfeld <prosenfeld@micron.com> Paul Rosenfeld <dramninjas@gmail.com>
@@ -333,39 +308,29 @@ Po-Hao Su <supohaosu@gmail.com>
 Polina Dudnik <pdudnik@cs.wisc.edu> Polina Dudnik <pdudnik@gmail.com>
 Polydoros Petrakis <ppetrak@ics.forth.gr>
 Pouya Fotouhi <pfotouhi@ucdavis.edu> Pouya Fotouhi <Pouya.Fotouhi@amd.com>
-Prajwal Hegde <prhegde@wisc.edu>
 Prakash Ramrakhyani <prakash.ramrakhyani@arm.com> Prakash Ramrakhani <Prakash.Ramrakhani@arm.com>
 Prakash Ramrakhyani <prakash.ramrakhyani@arm.com> Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com>
 Pritha Ghoshal <pritha9987@tamu.edu>
-Pu (Luke) Yi <lukeyi@stanford.edu>
 Quentin Forcioli <quentin.forcioli@telecom-paris.fr>
 Radhika Jagtap <radhika.jagtap@arm.com> Radhika Jagtap <radhika.jagtap@ARM.com>
 Rahul Thakur <rjthakur@google.com>
-Rajarshi Das <drajarsh@gmail.com>
-Ranganath (Bujji) Selagamsetty <bujji.selagamsetty@amd.com> BujSet <ranganath1000@gmail.com>
-Razeza <borisov.dn@phystech.edu>
-Reiley Jeapaul <reiley.jeyapaul@arm.com> Reiley Jeapaul <Reiley.Jeyapaul@arm.com>
+Reiley Jeapaul <Reiley.Jeyapaul@arm.com>
 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
+Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com>
 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>
 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> Rekai <Rekai.GonzalezAlberquilla@arm.com>
 Rene de Jong <rene.dejong@arm.com>
 Ricardo Alves <ricardo.alves@arm.com>
 Richard Cooper <richard.cooper@arm.com>
-Richard Strong <rstrong@hp.com> Richard D. Strong <r.d.strong@gmail.com>
+Richard D. Strong <r.d.strong@gmail.com>
 Richard Strong <rstrong@hp.com> Richard Strong <r.d.strong@gmail.com>
 Richard Strong <rstrong@hp.com> Richard Strong <rstrong@cs.ucsd.edu>
 Richard Strong <rstrong@hp.com> Rick Strong <rstrong@cs.ucsd.edu>
 Rico Amslinger <rico.amslinger@informatik.uni-augsburg.de>
 Riken Gohil <Riken.Gohil@arm.com>
 Rizwana Begum <rb639@drexel.edu>
-Robert Hauser <85344819+robhau@users.noreply.github.com>
 Robert Kovacsics <rmk35@cl.cam.ac.uk>
 Robert Scheffel <robert.scheffel1@tu-dresden.de> Robert <robert.scheffel1@tu-dresden.de>
-Rocky Tatiefo <rtatiefo@google.com>
-Roger Chang <rogerycchang@google.com> rogerchang23424 <rogerycchang@google.com>
-Roger Chang <rogerycchang@google.com> rogerchang23424 <32214817+rogerchang23424@users.noreply.github.com>
-Roger Chang <rogerycchang@google.com> rogerchang23424 <aucixw45876@gmail.com>
-Roger Chang <rogerycchang@google.com> Yu-Cheng Chang <rogerycchang@google.com>
 Rohit Kurup <rohit.kurup@arm.com>
 Ron Dreslinski <rdreslin@umich.edu> Ronald Dreslinski <rdreslin@umich.edu>
 Ruben Ayrapetyan <ruben.ayrapetyan@arm.com>
@@ -377,21 +342,23 @@ sacak32 <byrakocalan99@gmail.com>
 Sampad Mohapatra <sampad.mohapatra@gmail.com>
 Samuel Grayson <sam@samgrayson.me>
 Samuel Stark <samuel.stark2@arm.com>
+Sandipan Das <31861871+sandip4n@users.noreply.github.com>
 Sandipan Das <sandipan@linux.ibm.com> Sandipan Das <31861871+sandip4n@users.noreply.github.com>
 Santi Galan <santi.galan@metempsy.com>
 Sascha Bischoff <sascha.bischoff@arm.com> Sascha Bischoff <sascha.bischoff@ARM.com>
-Saúl Adserias <33020671+saul44203@users.noreply.github.com>
+Sascha Bischoff <sascha.bischoff@arm.com> Sascha Bischoff <Sascha.Bischoff@ARM.com>
 Sean McGoogan <Sean.McGoogan@arm.com>
 Sean Wilson <spwilson2@wisc.edu>
 Sergei Trofimov <sergei.trofimov@arm.com>
 Severin Wischmann <wiseveri@student.ethz.ch> Severin Wischmann ext:(%2C%20Ioannis%20Ilkos%20%3Cioannis.ilkos09%40imperial.ac.uk%3E) <wiseveri@student.ethz.ch>
 Shawn Rosti <shawn.rosti@gmail.com>
 Sherif Elhabbal <elhabbalsherif@gmail.com>
-Shivani Parekh <shparekh@ucdavis.edu> Shivani <shparekh@ucdavis.edu>
+Shivani Parekh <shparekh@ucdavis.edu>
+Shivani <shparekh@ucdavis.edu>
 Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
-Simon Park <seminpark@google.com>
 Somayeh Sardashti <somayeh@cs.wisc.edu>
-Sooraj Puthoor <puthoorsooraj@gmail.com> Sooraj Puthoor <Sooraj.Puthoor@amd.com>
+Sooraj Puthoor <puthoorsooraj@gmail.com>
+Sooraj Puthoor <Sooraj.Puthoor@amd.com>
 Sophiane Senni <sophiane.senni@gmail.com>
 Soumyaroop Roy <sroy@cse.usf.edu>
 Srikant Bharadwaj <srikant.bharadwaj@amd.com>
@@ -403,6 +370,7 @@ Steve Raasch <sraasch@umich.edu>
 Steve Reinhardt <stever@gmail.com> Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E) <stever@gmail.com>
 Steve Reinhardt <stever@gmail.com> Steve Reinhardt <stever@eecs.umich.edu>
 Steve Reinhardt <stever@gmail.com> Steve Reinhardt <steve.reinhardt@amd.com>
+Steve Reinhardt <stever@gmail.com> Steve Reinhardt <Steve.Reinhardt@amd.com>
 Stian Hvatum <stian@dream-web.no>
 Sudhanshu Jha <sudhanshu.jha@arm.com>
 Sujay Phadke <electronicsguy123@gmail.com>
@@ -410,18 +378,16 @@ Sungkeun Kim <ksungkeun84@tamu.edu>
 Swapnil Haria <swapnilster@gmail.com> Swapnil Haria <swapnilh@cs.wisc.edu>
 Taeho Kgil <tkgil@umich.edu>
 Tao Zhang <tao.zhang.0924@gmail.com>
-Thilo Vörtler <thilo.voertler@coseda-tech.com> root <thilo.voertler@coseda-tech.com>
 Thomas Grass <Thomas.Grass@ARM.com>
 Tiago Mück <tiago.muck@arm.com> Tiago Muck <tiago.muck@arm.com>
-Tiberiu Bucur <36485854+TiberiuBucur@users.noreply.github.com>
 Tim Harris <tharris@microsoft.com>
 Timothy Hayes <timothy.hayes@arm.com>
 Timothy M. Jones <timothy.jones@arm.com> Timothy Jones <timothy.jones@cl.cam.ac.uk>
 Timothy M. Jones <timothy.jones@arm.com> Timothy M. Jones <timothy.jones@cl.cam.ac.uk>
 Timothy M. Jones <timothy.jones@arm.com> Timothy M. Jones <tjones1@inf.ed.ac.uk>
 Tom Jablin <tjablin@gmail.com>
-Tom Rollet <tom.rollet@huawei.com>
 Tommaso Marinelli <tommarin@ucm.es>
+Tom Rollet <tom.rollet@huawei.com>
 Tong Shen <endlessroad@google.com>
 Tony Gutierrez <anthony.gutierrez@amd.com> Anthony Gutierrez <atgutier@umich.edu>
 Travis Boraten <travis.boraten@amd.com>
@@ -435,7 +401,6 @@ Victor Garcia <victor.garcia@arm.com>
 Vilas Sridharan <vilas.sridharan@gmail.com>
 Vincentius Robby <acolyte@umich.edu>
 Vince Weaver <vince@csl.cornell.edu>
-Vishnu Ramadas <vramadas@outlook.com>
 vramadas95 <vramadas@wisc.edu>
 vsoria <victor.soria@bsc.es>
 Wade Walker <wade.walker@arm.com>
@@ -444,16 +409,14 @@ Weiping Liao <weipingliao@google.com>
 Wende Tan <twd2@163.com>
 Wendy Elsasser <wendy.elsasser@arm.com>
 William Wang <william.wang@arm.com> William Wang <William.Wang@arm.com>
+William Wang <william.wang@arm.com> William Wang <William.Wang@ARM.com>
 Willy Wolff <willy.mh.wolff.ml@gmail.com>
 Wing Li <wingers@google.com>
-wmin0 <wmin0@hotmail.com>
 Xiangyu Dong <rioshering@gmail.com>
 Xianwei Zhang <xianwei.zhang.@amd.com> Xianwei Zhang <xianwei.zhang@amd.com>
 Xiaoyu Ma <xiaoyuma@google.com>
 Xin Ouyang <xin.ouyang@streamcomputing.com>
 Xiongfei <xiongfei.liao@gmail.com>
-Xuan Hu <huxuan@bosc.ac.cn>
-Yan Lee <yanlee@google.com>
 Yasuko Eckert <yasuko.eckert@amd.com>
 Yen-lin Lai <yenlinlai@google.com>
 Yifei Liu <liu.ad2039@gmail.com>
@@ -463,10 +426,7 @@ Yuan Yao <yuanyao@seas.harvard.edu>
 Yuetsu Kodama <yuetsu.kodama@riken.jp> yuetsu.kodama <yuetsu.kodama@riken.jp>
 Yu-hsin Wang <yuhsingw@google.com>
 Zhang Zheng <perise@gmail.com>
-Zhantong Qiu <ztqiu@ucdavis.edu> studyztp <studyztp@gmail.com>
+Zhantong Qiu <ztqiu@ucdavis.edu>
 Zhengrong Wang <seanzw@ucla.edu> seanzw <seanyukigeek@gmail.com>
-Zhengrong Wang <seanzw@ucla.edu> Zhengrong Wang <seanyukigeek@gmail.com>
 zhongchengyong <zhongcy93@gmail.com>
 Zicong Wang <wangzicong@nudt.edu.cn>
-Zixian Cai <2891235+caizixian@users.noreply.github.com>
-zmckevitt <zack.mckevitt@gmail.com>

.pre-commit-config.yaml

@@ -1,4 +1,3 @@
----
 # Copyright (c) 2022 Arm Limited
 # All rights reserved.
 #
@@ -34,71 +33,57 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-minimum_pre_commit_version: '2.18'
+minimum_pre_commit_version: "2.18"
 
 default_language_version:
-    python: python3
+  python: python3
 
 exclude: |
-    (?x)^(
-      ext/(?!testlib/).*|
-      build/.*|
-      src/systemc/ext/.*|
-      src/systemc/tests/.*/.*|
-      src/python/m5/ext/pyfdt/.*|
-      tests/.*/ref/.*
-    )$
+  (?x)^(
+    ext/.*|
+    build/.*|
+    src/systemc/ext/.*|
+    src/systemc/tests/.*/.*|
+    src/python/m5/ext/pyfdt/.*|
+    tests/.*/ref/.*
+  )$
 
-default_stages: [pre-commit]
+default_stages: [commit]
 
 repos:
-    - repo: https://github.com/pre-commit/pre-commit-hooks
-      rev: v5.0.0
-      hooks:
-          - id: trailing-whitespace
-          - id: end-of-file-fixer
-          - id: check-json
-          - id: check-yaml
-          - id: check-added-large-files
-          - id: mixed-line-ending
-            args: [--fix=lf]
-          - id: check-ast
-          - id: check-case-conflict
-          - id: check-merge-conflict
-          - id: check-symlinks
-          - id: destroyed-symlinks
-          - id: requirements-txt-fixer
-    - repo: https://github.com/PyCQA/isort
-      rev: 5.13.2
-      hooks:
-          - id: isort
-    - repo: https://github.com/jumanjihouse/pre-commit-hook-yamlfmt
-      rev: 0.2.3
-      hooks:
-          - id: yamlfmt
-    - repo: https://github.com/psf/black
-      rev: 24.10.0
-      hooks:
-          - id: black
-    - repo: https://github.com/asottile/pyupgrade
-      rev: v3.17.0
-      hooks:
-          - id: pyupgrade
-            # Python 3.8 is the earliest version supported.
-            # We therefore conform to the standards compatible with 3.8+.
-            args: [--py38-plus]
-    - repo: local
-      hooks:
-          - id: gem5-style-checker
-            name: gem5 style checker
-            entry: util/git-pre-commit.py
-            always_run: true
-            exclude: .*
-            language: system
-            description: The gem5 style checker hook.
-          - id: gem5-commit-msg-checker
-            name: gem5 commit msg checker
-            entry: util/git-commit-msg.py
-            language: system
-            stages: [commit-msg]
-            description: The gem5 commit message checker hook.
+- repo: https://github.com/pre-commit/pre-commit-hooks
+  rev: v4.3.0
+  hooks:
+  - id: trailing-whitespace
+  - id: end-of-file-fixer
+  - id: check-json
+  - id: check-yaml
+  - id: check-added-large-files
+  - id: mixed-line-ending
+    args: [--fix=lf]
+  - id: check-case-conflict
+- repo: https://github.com/psf/black
+  rev: 22.6.0
+  hooks:
+    - id: black
+- repo: local
+  hooks:
+  - id: gem5-style-checker
+    name: gem5 style checker
+    entry: util/git-pre-commit.py
+    always_run: true
+    exclude: ".*"
+    language: system
+    description: 'The gem5 style checker hook.'
+  - id: gem5-commit-msg-checker
+    name: gem5 commit msg checker
+    entry: ext/git-commit-msg
+    language: system
+    stages: [commit-msg]
+    description: 'The gem5 commit message checker hook.'
+  - id: gerrit-commit-msg-job
+    name: gerrit commit message job
+    entry: util/gerrit-commit-msg-hook
+    language: system
+    stages: [commit-msg]
+    description: 'Adds Change-ID to the commit message. Needed by Gerrit.'

.vscode/settings.json

@@ -1,7 +0,0 @@
-{
-    "python.analysis.extraPaths": [
-        "src/python",
-        "ext",
-        "tests"
-    ]
-}

MAINTAINERS.yaml

@@ -1,23 +1,23 @@
----
 # See CONTRIBUTING.md for details of gem5's contribution process.
 #
 # This file contains a list of gem5's subsystems and their
-# maintainers. The key used to identify a subsystem should be used
-# as a tag in commit messages targeting that subsystem. Via our GitHub
-# Pull Request system (https://github.com/gem5/gem5/pulls) a maintainer
-# of the subsystem impacted by a pull request contribution will be added
-# as an assignee to that pull request. Their role is be to referee the
-# contribution (add a review, assign reviewers, suggest changes, etc.), then
-# merge the contribution into the gem5 develop branch when they are satisfied
-# with the change.
+# maintainers. The key used to identifity a subsystem should be used
+# as a tag in commit messages targetting that subsystem. At least one
+# (not all) of these maintainers must review the patch before it can
+# be pushed. These people will automatically be emailed when you
+# upload the patch to Gerrit (https://gem5-review.googlesource.com).
+# These subsystem keys mostly follow the directory structure.
 #
-# Maintainers assigned to a pull request are expected to acknowledge their
-# assignment in 2 business days and to fully begin refereeing the contribution
-# within a business week.
+# Maintainers have the following responsibilities:
+# 1. That at least one maintainer of each subsystem reviews all
+#    changes to that subsystem (they will be automatically tagged and
+#    emailed on each new change).
+# 2. They will complete your reviews in a timely manner (within a few
+#    business days).
+# 3. They pledge to uphold gem5's community standards and its code of
+#    conduct by being polite and professional in their code
+#    reviews. See CODE-OF-CONDUCT.md.
 #
-# Maintainers pledge to uphold gem5's community standards and its code of
-# conduct by being polite and professional in their interactions with
-# contributors. See CODE-OF-CONDUCT.md.
 #
 # Entries in this file have the following format:
 #   key:
@@ -27,257 +27,310 @@
 #     maintainers:
 #       - John Doe <john.doe@gem5.org>
 #       - Jane Doe <jane.doe@gem5.org>
-#     experts:
-#       - Jack Doe <jack.doe@gem5org>
-#       - Jill Doe <jill.doe@gem5org>
+#
 #
 # The status field should have one of the following values:
 #   - maintained: The component has an active maintainer.
 #   - orphaned: The component is looking for a new owner.
-#
-# The experts field is optional and used to identify people who are
-# knowledgeable about the subsystem but are not responsible for it. Those
-# listed as an expert are typically good to add as a reviewer for pull requests
-# targeting that subsystem.
+
+
+pmc:
+  desc: >-
+    PMC Members (general maintainers):
+  status: maintained
+  maintainers:
+    - Andreas Sandberg <andreas.sandberg@arm.com>
+    - Brad Beckmann <bradford.beckmann@gmail.com>
+    - David Wood <david@cs.wisc.edu>
+    - Gabe Black <gabe.black@gmail.com>
+    - Giacomo Travaglini <giacomo.travaglini@arm.com>
+    - Jason Lowe-Power <jason@lowepower.com> (chair)
+    - Matt Sinclair <sinclair@cs.wisc.edu>
+    - Tony Gutierrez <anthony.gutierrez@amd.com>
+    - Steve Reinhardt <stever@gmail.com>
 
 arch:
-    desc: >-
-        General architecture-specific components
-    status: orphaned
+  desc: >-
+    General architecture-specific components
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
 
 arch-arm:
-    status: maintained
-    maintainers:
-        - Giacomo Travaglini <giacomo.travaglini@arm.com>
-        - Andreas Sandberg <andreas.sandberg@arm.com>
+  status: maintained
+  maintainers:
+    - Andreas Sandberg <andreas.sandberg@arm.com>
+    - Giacomo Travaglini <giacomo.travaglini@arm.com>
+
+arch-gcn3:
+  status: maintained
+  maintainers:
+    - Matt Poremba <matthew.poremba@amd.com>
+    - Matt Sinclair <sinclair@cs.wisc.edu>
 
 arch-vega:
-    status: maintained
-    maintainers:
-        - Matt Sinclair <sinclair@cs.wisc.edu>
-        - Matt Poremba <matthew.poremba@amd.com>
+  status: maintained
+  maintainers:
+    - Matt Poremba <matthew.poremba@amd.com>
+    - Matt Sinclair <sinclair@cs.wisc.edu>
 
 arch-mips:
-    status: orphaned
+  status: orphaned
 
 arch-power:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Boris Shingarov <shingarov@labware.com>
 
 arch-riscv:
-    status: orphaned
+  status: orphaned
 
 arch-sparc:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
 
 arch-x86:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
 
 base:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
+    - Daniel Carvalho <odanrc@yahoo.com.br>
 
 base-stats:
-    status: orphaned
+  status: orphaned
 
 configs:
-    status: orphaned
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
+  status: maintained
+  maintainers:
+    - Jason Lowe-Power <jason@lowepower.com>
 
 cpu:
-    desc: >-
-        General changes to all CPU models (e.g., BaseCPU)
-    status: orphaned
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
+  desc: >-
+    General changes to all CPU models (e.g., BaseCPU)
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
+    - Jason Lowe-Power <jason@lowepower.com>
 
 cpu-kvm:
-    status: maintained
-    maintainers:
-        - Andreas Sandberg <andreas.sandberg@arm.com>
+  status: maintained
+  maintainers:
+    - Andreas Sandberg <andreas.sandberg@arm.com>
 
 cpu-minor:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Zhengrong Wang <seanyukigeek@gmail.com>
 
 cpu-o3:
-    status: orphaned
+  status: orphaned
 
 cpu-simple:
-    status: orphaned
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
+  status: maintained
+  maintainers:
+    - Jason Lowe-Power <jason@lowepower.com>
+    - Gabe Black <gabe.black@gmail.com>
 
 dev:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
 
 dev-hsa:
-    status: maintained
-    maintainers:
-        - Matt Poremba <matthew.poremba@amd.com>
-        - Matt Sinclair <sinclair@cs.wisc.edu>
+  status: maintained
+  maintainers:
+    - Matt Poremba <matthew.poremba@amd.com>
 
 dev-amdgpu:
-    status: maintained
-    maintainers:
-        - Matt Poremba <matthew.poremba@amd.com>
-        - Matt Sinclair <sinclair@cs.wisc.edu>
+  status: maintained
+  maintainers:
+    - Matt Poremba <matthew.poremba@amd.com>
 
 dev-virtio:
-    status: maintained
-    maintainers:
-        - Andreas Sandberg <andreas.sandberg@arm.com>
+  status: maintained
+  maintainers:
+    - Andreas Sandberg <andreas.sandberg@arm.com>
 
 dev-arm:
-    status: maintained
-    maintainers:
-        - Giacomo Travaglini <giacomo.travaglini@arm.com>
-        - Andreas Sandberg <andreas.sandberg@arm.com>
+  status: maintained
+  maintainers:
+    - Andreas Sandberg <andreas.sandberg@arm.com>
+    - Giacomo Travaglini <giacomo.travaglini@arm.com>
 
 doc:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
 
 ext:
-    desc: >-
-        Components external to gem5
-    status: orphaned
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
+  desc: >-
+    Components external to gem5
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
+    - Jason Lowe-Power <jason@lowepower.com>
 
 ext-testlib:
-    status: orphaned
-    experts:
-        - Bobby R. Bruce <bbruce@ucdavis.edu>
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
+    - Hoa Nguyen <hoanguyen@ucdavis.edu>
 
 fastmodel:
-    desc: >-
-        Changes relating to ARM Fast Models
-    status: orphaned
+  desc: >-
+    Changes relating to ARM Fast Models
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
 
 gpu-compute:
-    status: maintained
-    maintainers:
-        - Matt Poremba <matthew.poremba@amd.com>
-        - Matt Sinclair <sinclair@cs.wisc.edu>
+  status: maintained
+  maintainers:
+    - Matt Poremba <matthew.poremba@amd.com>
+    - Matt Sinclair <sinclair@cs.wisc.edu>
 
 learning-gem5:
-    desc: >-
-        The code and configs for the Learning gem5 book
-    status: orphaned
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
-        - Bobby R. Bruce <bbruce@ucdavis.edu>
+  desc: >-
+    The code and configs for the Learning gem5 book
+  status: maintained
+  maintainers:
+    - Jason Lowe-Power <jason@lowepower.com>
 
 stdlib:
-    desc: >-
-        The gem5 standard library found under `src/python/gem5`
-    status: maintained
-    maintainers:
-        - Bobby R. Bruce <bbruce@ucdavis.edu>
+  desc: >-
+    The gem5 standard library found under `src/python/gem5`
+  status: maintained
+  maintainers:
+    - Bobby R. Bruce <bbruce@ucdavis.edu>
 
 mem:
-    desc: >-
-        General memory system (e.g., XBar, Packet)
-    status: orphaned
+  desc: >-
+    General memory system (e.g., XBar, Packet)
+  status: maintained
+  maintainers:
+    - Nikos Nikoleris <nikos.nikoleris@arm.com>
 
 mem-cache:
-    desc: >-
-        Classic caches and coherence
-    status: orphaned
+  desc: >-
+    Classic caches and coherence
+  status: maintained
+  maintainers:
+    - Nikos Nikoleris <nikos.nikoleris@arm.com>
+    - Daniel Carvalho <odanrc@yahoo.com.br>
 
 mem-dram:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Nikos Nikoleris <nikos.nikoleris@arm.com>
 
 mem-garnet:
-    desc: >-
-        Garnet subcomponent of Ruby
-    status: orphaned
+  desc: >-
+    Garnet subcomponent of Ruby
+  status: maintained
+  maintainers:
+    - Srikant Bharadwaj <srikant.bharadwaj@amd.com>
 
 mem-ruby:
-    desc: >-
-        Ruby structures and protocols
-    status: maintained
-    maintainers:
-        - Matt Sinclair <sinclair@cs.wisc.edu>
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
+  desc: >-
+    Ruby structures and protocols
+  status: maintained
+  maintainers:
+    - Jason Lowe-Power <jason@lowepower.com>
+    - Matt Sinclair <sinclair@cs.wisc.edu>
 
 misc:
-    desc: >-
-        Anything outside of the other categories
-    status: orphaned
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
+  desc: >-
+    Anything outside of the other categories
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
+    - Jason Lowe-Power <jason@lowepower.com>
 
 python:
-    desc: >-
-        Python SimObject wrapping and infrastructure
-    status: orphaned
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
-        - Andreas Sandberg <andreas.sandberg@arm.com>
+  desc: >-
+    Python SimObject wrapping and infrastructure
+  status: maintained
+  maintainers:
+    - Andreas Sandberg <andreas.sandberg@arm.com>
+    - Jason Lowe-Power <jason@lowepower.com>
 
 resources:
-    desc: >-
-        The gem5-resources repo with auxiliary resources for simulation
-    status: maintained
-    maintainers:
-        - Bobby R. Bruce <bbruce@ucdavis.edu>
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
+  desc: >-
+    The gem5-resources repo with auxiliary resources for simulation
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
+    - Jason Lowe-Power <jason@lowepower.com>
 
 scons:
-    desc: >-
-        Build system
-    status: orphaned
+  desc: >-
+    Build system
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
 
 sim:
-    desc: >-
-        General simulation components
-    status: orphaned
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
+  desc: >-
+    General simulation components
+  status: maintained
+  maintainers:
+    - Jason Lowe-Power <jason@lowepower.com>
 
 sim-se:
-    desc: >-
-        Syscall emulation
-    status: orphaned
+  desc: >-
+    Syscall emulation
+  status: orphaned
 
 system-arm:
-    status: maintained
-    maintainers:
-        - Giacomo Travaglini <giacomo.travaglini@arm.com>
-        - Andreas Sandberg <andreas.sandberg@arm.com>
+  status: maintained
+  maintainers:
+    - Andreas Sandberg <andreas.sandberg@arm.com>
+    - Giacomo Travaglini <giacomo.travaglini@arm.com>
 
 systemc:
-    desc: >-
-        Code for the gem5 SystemC implementation and interface
-    status: orphaned
+  desc: >-
+    Code for the gem5 SystemC implementation and interface
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
 
 tests:
-    desc: >-
-        testing changes
-    status: maintained
-    maintainers:
-        - Bobby R. Bruce <bbruce@ucdavis.edu>
+  desc: >-
+    testing changes
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
 
 util:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
 
 util-docker:
-    status: maintained
-    maintainers:
-        - Bobby R. Bruce <bbruce@ucdavis.edu>
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
 
 util-m5:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Gabe Black <gabe.black@gmail.com>
 
 util-gem5art:
-    status: orphaned
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
+    - Jason Lowe-Power <jason@lowepower.com>
 
 website:
-    desc: >-
-        The gem5-website repo which contains the gem5.org site
-    status: maintained
-    maintainers:
-        - Bobby R. Bruce <bbruce@ucdavis.edu>
-    experts:
-        - Jason Lowe-Power <jason@lowepower.com>
+  desc: >-
+    The gem5-website repo which contains the gem5.org site
+  status: maintained
+  maintainers:
+    - Bobby Bruce <bbruce@ucdavis.edu>
+    - Hoa Nguyen <hoanguyen@ucdavis.edu>

README.md

@@ -10,15 +10,6 @@ system software changes, and compile-time and run-time system optimizations.
 
 The main website can be found at <http://www.gem5.org>.
 
-## Testing status
-
-**Note**: These regard tests run on the develop branch of gem5:
-<https://github.com/gem5/gem5/tree/develop>.
-
-[![Daily Tests](https://github.com/gem5/gem5/actions/workflows/daily-tests.yaml/badge.svg?branch=develop)](https://github.com/gem5/gem5/actions/workflows/daily-tests.yaml)
-[![Weekly Tests](https://github.com/gem5/gem5/actions/workflows/weekly-tests.yaml/badge.svg?branch=develop)](https://github.com/gem5/gem5/actions/workflows/weekly-tests.yaml)
-[![Compiler Tests](https://github.com/gem5/gem5/actions/workflows/compiler-tests.yaml/badge.svg?branch=develop)](https://github.com/gem5/gem5/actions/workflows/compiler-tests.yaml)
-
 ## Getting started
 
 A good starting point is <http://www.gem5.org/about>, and for
@@ -38,8 +29,8 @@ Once you have all dependencies resolved, execute
 `scons build/ALL/gem5.opt` to build an optimized version of the gem5 binary
 (`gem5.opt`) containing all gem5 ISAs. If you only wish to compile gem5 to
 include a single ISA, you can replace `ALL` with the name of the ISA. Valid
-options include `ARM`, `NULL`, `MIPS`, `POWER`, `RISCV`, `SPARC`, and `X86`
-The complete list of options can be found in the build_opts directory.
+options include `ARM`, `NULL`, `MIPS`, `POWER`, `SPARC`, and `X86` The complete
+list of options can be found in the build_opts directory.
 
 See https://www.gem5.org/documentation/general_docs/building for more
 information on building gem5.
@@ -94,6 +85,6 @@ or start discussions. To join the mailing list please visit
 
 ## Contributing to gem5
 
-We hope you enjoy using gem5. When appropriate we advise sharing your
+We hope you enjoy using gem5. When appropriate we advise charing your
 contributions to the project. <https://www.gem5.org/contributing> can help you
 get started. Additional information can be found in the CONTRIBUTING.md file.

RELEASE-NOTES.md

@@ -1,519 +1,3 @@
-# Version 24.1.0.2
-
-**[HOTFIX]** Adds PR <https://github.com/gem5/gem5/pull/1930> as a hotfix to v24.1.0.
-
-This fixes a bug which was was causing the CHI coherence protocol to fail in multi-core simulations.
-The fix sets the `RubySystem` pointer when the TBE is allocated, instead of when `set_tbe` is performed, thus ensuring that the `RubySystem` pointer is set before the TBE is used.
-
-# Version 24.1.0.1
-
-**[HOTFIX]** This hotfix release applies the following:
-
-* Generalization of the class types in CHI RNF/MN generators thus fixing an issue with missing attributes when using the CHI protocol.
-PR: <https://github.com/gem5/gem5/pull/1851>.
-* Add Sphinx documentation for the gem5 standard library.
-This is largely generated from Python docstrings.
-See "docs/README" for more information on building and deploying Sphinx documentation.
-PR: <https://github.com/gem5/gem5/pull/335>.
-* Add missing `RubySystem` member and related methods in `PerfectCacheMemory`'s entries.
-This was causing assertions to trigger in "src/mem/ruby/commonNetDest.cc".
-PR: <https://github.com/gem5/gem5/pull/1864>.
-* Add `useSecondaryLoadLinked` function to "src/mem/ruby/slicc_interface/ProtocolInfo.hh".
-This fixes a bug which was introduced after the removal of the `PROTOCOL_MESI_Two_Level` and `PROTOCOL_MESI_Three_Level` MACROs in v24.1.0.0.
-These MACROs were being used to infer if `Load_Linked` requests are sent to the Ruby protocol or not.
-The `useSecondaryLoadLinked` function has been introduced to specify this directly where needed.
-PR: <https://github.com/gem5/gem5/pull/1865>.
-
-# Version 24.1
-
-## User facing changes
-
-* The [behavior of the statistics `simInsts` and `simOps` has been changed](https://github.com/gem5/gem5/pull/1615).
-  * They now reset to zero when m5.stats.reset() is called.
-  * Previously, they incorrectly did not reset and would increase monotonically throughout the simulation.
-  * The statistics `hostInstRate` and `hostOpRate` are also affected by this change, as they are calculated using simInsts and simOps respectively.
-
-* Instances of kB, MB, and GB have been changed to KiB, MiB, and GiB for memory and cache sizes #1479
-  * A warning has also been added for usages of kB, MB, and GB.
-  * Please use KiB, MiB, and GiB in the future.
-
-* Random number generator is no longer shared across components. This may modify simulation results. #1534
-
-### gem5 Standard Library
-
-* SE mode has been added to X86Board, X86DemoBoard, and RiscvBoard #1702
-* ArmDemoBoard and RiscvDemoBoard have been added to the standard library #1478 #1490
-* The values in the X86DemoBoard have been modified to make it more similar to the other DemoBoards #1618
-
-### Prefetchers
-
-* The [behavior of the`StridePrefetcher` has been altered](https://github.com/gem5/gem5/pull/1449) as follows:
-  * The addresses used to compute the stride has been changed from word aligned addresses to cache line aligned addresses.
-  * It returns if the stride does not match, as opposed to issuing prefetching using the new stride --- the previous, incorrect behavior.
-  * Returns if the new stride is 0, indicating multiple reads from the same cache line.
-* Fix implementation of Best Offset Prefetcher #1403
-* Add SMS Prefetcher
-
-### Configuration scripts
-
-* Update the full system gem5 Standard Library example scripts to use Ubuntu 24.04 disk images #1491
-* Add RV32 option to configs/example/riscv/fs_linux.py #1312
-* Other updates to configs/example/riscv/fs_linux.py #1753
-
-### Multisim
-
-* simerr.txt and simout.txt now output into the correct sub-directory when -re is passed #1551
-
-### Compiler and OS support
-
-As of this release, gem5 supports Clang versions 14 through 18 and GCC versions 10 through 14.
-Other versions may work, but they are not regularly tested.
-
-### Multiple Ruby Protocols in a Single Build
-
-There are many developer facing / API changes to enable Ruby multiple protocols in a single build.
-The most notable changes are:
-
-* Removes the RubySlicc_interfaces.slicc file from the SLICC includes of
-every protocol.
-  * Changes required: If you have a custom protocol, you will need to remove the line `include "RubySlicc_interfaces.slicc"` from your .slicc file.
-* Updates the build configurations variables
-  * **USER FACING CHANGE**: The Ruby protocols in Kconfig have changed names (they are now the same case as the SLICC file names), and in addition,  So, after this commit, your build configurations need to be updated. You can do so by running `scons menuconfig <build dir>` and selecting the right ruby options. Alternatively, if you're using a `build_opts` file, you can run `scons defconfig build/<ISA> build_opts/<ISA>` which should update your config correctly.
-  * **USER FACING CHANGE**: The the "build_opts/ALL" build spec has been updated to include all Ruby protocols . As such, gem5 compilations of the "ALL" compilation target will include all gem5 Ruby protocols (previously just MESI_Two_Level).
-  * A "build_opts/NULL_ALL_RUBY" build spec has been added to include all Ruby protocols for a "NULL ISA" build . This is useful for testing Ruby protocols without the overhead of a full ISA and is used in gem5's traffic generator tests.
-  * A "build_opts/ARM_X86" build spec has been added due to a unique restriction in the "tests/gem5/fs/linux/arm" tests which requires a compilation of gem5 with both ARM and X86 and solely the MESI_Two_Level protocol.
-
-### Multiple RubySystem objects in a simulation
-
-Simulation configurations can now create multiple `RubySystem`s in the same simulation.
-Previously this was not possible due to `RubySystem` sharing variables across all `RubySystems` (e.g., cache line size).
-Allowing this feature requires developer facing changes for custom Ruby protocols.
-The most common changes will be:
-
-* Modify your custom protocol SLICC files, replace any instances of `RubySystem::foo()` with `m_ruby_system->foo()`, and recompile. `m_ruby_system` is automatically set by SLICC generated code.
-* If your custom protocol contains local `WriteMask` declarations (e.g., `WriteMask tmp_mask;`), modify the protocol so that `tmp_mask.setBlockSize(...)` is called. Use the block size of the `RubySystem` here (e.g., you can use `other_mask.getBlockSize()` or get block size from another object).
-* Modify your python configurations to assign the parameter `ruby_system` for the python classes `RubySequencer`, `RubyDirectoryMemory`, and `RubyPortProxy` or any derived classes. You will receive an error at the start of gem5 if this is not done.
-* If your python configuration uses a `RubyPrefetcher`, modify the configuration to assign the `block_size` parameter to the cache line size of the `RubySystem` the prefetcher is part of.
-
-The complete list of changes are:
-
-* `AbstractCacheEntry`, `ALUFreeListArray`, `DataBlock`, `Message`, `PerfectCacheMemory`, `PersistentTable`, `TBETable`, `TimerTable`, and `WriteMask` classes now require the cache line size to be explicitly set. This is handled automatically by the SLICC parser but must be done explicitly in C++ code by calling `setBlockSize()`.
-* `RubyPrefetcher` now requires `block_size` be assigned in python configurations.
-* `CacheMemory` now requires a pointer to the `RubySystem` to be set. This is handled automatically by the SLICC parser but must be done explicitly in C++ code by calling `setRubySystem()`.
-* `RubyDirectoryMemory`, `RubyPortProxy`, and `RubySequencer` now require a pointer to the `RubySystem` to be set by python configurations. If you have custom protocols using `DirectoryMemory` or derived classes from it, the `ruby_system` parameter must be set in the python configuration.
-* `ALUFreeListArray` and `BankedArray` now require a clock period to be set in C++ using `setClockPeriod()` and no longer require a pointer to the `RubySystem`.
-* You may no longer call `RubySystem::getBlockSizeBytes()`, `RubySystem::getBlockSizeBits()`, etc. You must have a pointer to the `RubySystem` you are a part of and call, for example, `ruby_system->getBlockSizeBytes()`.
-* `MessageBuffer::enqueue()` has two new parameters indicating if the `RubySystem` has randomization and warmup enabled. You must explicitly specify these values now.
-
-## ArmISA changes/improvements
-
-### Architectural extensions
-
-Architectural support for the following extensions:
-
-* FEAT_TTST
-* FEAT_XS
-
-### Bugfixes
-
-* Add support of AArch32 VRINTN/X/A/Z/M/P instructions
-* Add support of AArch32 VCVTA/P/N/M instructions
-* The following syscalls have been added in SE mode
-  * readv
-  * poll
-  * pread64
-  * pwrite64
-  * truncate64
-* The following syscalls have been fixed in SE mode when running on a 32bit HOST:
-  * getcwd
-  * lseek
-
-### CPU changes
-
-Before this release the Arm TLBs were using an hardcoded fully associative model with LRU replacement policy.
-The associativity and replacement policy of the Arm TLBs are now configurable with the IndexingPolicy and ReplacementPolicy classes by setting the indexing_policy and replacement_policy params.
-
-```python
-    indexing_policy = Param.TLBIndexingPolicy(
-        TLBSetAssociative(assoc=Parent.assoc, num_entries=Parent.size),
-        "Indexing policy of the TLB",
-    )
-    replacement_policy = Param.BaseReplacementPolicy(
-        LRURP(), "Replacement policy of the TLB"
-    )
-```
-
-While default behaviour is still LRU + FA, the L2 TLB in the ArmMMU (l2_shared) has been converted from being a fully associative structure into being a 5-way set associative.
-The default ArmMMU is therefore:
-
-```python
-    # L2 TLBs
-    l2_shared = ArmTLB(
-        entry_type="unified", size=1280, assoc=5, partial_levels=["L2"]
-    )
-
-    # L1 TLBs
-    itb = ArmTLB(entry_type="instruction", next_level=Parent.l2_shared)
-    dtb = ArmTLB(entry_type="data", next_level=Parent.l2_shared)
-```
-
-## AMBA CHI changes/improvements
-
-PR [1084](https://github.com/gem5/gem5/pull/1084) introduced two new CHI relevant classes.
-
-* The first one is the CHIGenericController. This is a purely C++ based / abstract interface of a Coherence Controller for ruby.
-It is meant to bypass SLICC and removes the limitation of using the gem5 Sequencer and associated data structures.
-* The second one is the CHI-TLM controller, which extends the aforementioned CHIGenericController. This is a bridge between the AMBA TLM 2.0 implementation of CHI [1](https://developer.arm.com/documentation/101459/latest) [2](https://developer.arm.com/Architectures/AMBA#Downloads) with the gem5 (ruby) one.
-
-In other words it translates AMBA CHI transactions into ruby messages (which are then forwarded to the MessageQueues)
-and vice versa.
-
-```text
-ARM::CHI::Payload,         CHIRequestMsg
-                     <-->  CHIDataMsg
-ARM::CHI::Phase            CHIResponseMsg
-                           CHIDataMsg
-```
-
-In this way it will be possible to connect external RNF models to the ruby interconnect via the CHI-TLM library
-
-## RISC-V ISA improvements
-
-* Use sign extend for all address generation #1316
-* Fix implicit int-to-float conversion in .isa files #1319
-* Implement Zcmp instructions #1432
-* Add support for riscv hardware probing syscall #1525
-* Add support for Zicbop extension #1710
-* Fix vector instruction assertion caused by speculative execution #1711
-
-## GPU model improvements
-
-The GPUFS model is now available in the standard library!
-There is a new `ViperBoard` in `gem5.prebuilt.viper`.
-This board is an initial implementation and will be improved in the next versions of gem5.
-There is an example script in `configs/example/gem5_library/x86-mi300x-gpu.py` that shows how to use the `ViperBoard`.
-See #1636.
-
-### Other GPU changes
-
-* Vega10 has been deprecated #1619
-* Replacement policy has been improved #1564
-* Swizzle multi-dword scratch requests now supported #1445
-* Many improvements to Vega implementation including memtime, SDWA, SDWAB, and DPP instructions #1350, #1378
-* Matrix Core Engines (AMD's equivalent to NVIDIA's TensorCores) now supported! #1248, #1700
-* Pannotia tests integrated into weekly tests #1584
-
-## Other Miscellaneous Changes
-
-### Other Ruby Related Changes
-
-* RubyHitMiss debug flag #1260
-* Prevent LL/SC livelock in MESI protocols #1399
-* Added files for [generating Sphinx documentation](https://github.com/gem5/gem5/pull/335) for the gem5 standard library.
-
-### Other
-
-* Looppoint analysis object #1419
-* Add global and local instruction trackers for raising instruction executed exit events with multi-core simulation #1433
-
-### Development
-
-* Removal of Gerrit Change-ID requirement #1486
-
-# Version 24.0.0.1
-
-**[HOTFIX]** Fixes a bug affecting the use of the `IndirectMemoryPrefetcher`, `SignaturePathPrefetcher`, `SignaturePathPrefetcherV2`, `STeMSPrefetcher`, and `PIFPrefetcher` SimObjects.
-Use of these resulted in gem5 crashing a gem5 crash with the error message "Need is_secure arg".
-
-The fix to this introduced to the gem5 develop branch in the <https://github.com/gem5/gem5/pull/1374> Pull Request.
-The commits in this PR were cherry-picked on the gem5 stable branch to create the v24.0.0.1 hotfix release.
-
-# Version 24.0
-
-gem5 Version 24.0 is the first major release of 2024.
-During this time there have been 298 pull requests merged, comprising of over 600 commits, from 56 unique contributors.
-
-## API and user-facing changes
-
-* The GCN3 GPU model has been removed in favor of the newer VEGA_X85 GPU model.
-* gem5 now supports building, running, and simulating Ubuntu 24.04.
-
-### Compiler and OS support
-
-As of this release gem5 support Clang version 6 to 16 and GCC version 10 to 13.
-While other compilers and versions may work, they are not regularly tested.
-
-gem5 now supports building, running, and simulating on Ubuntu 24.04.
-We continue to support 22.04 with 20.04 being deprecated in the coming year.
-The majority of our testing is done on Ubuntu LTS systems though Apple Silicon machines and other Linux distributions have also been used regularly during development.
-Improvements have been made to ensure a wider support of operating systems.
-
-## New features
-
-### gem5 MultiSim: Multiprocessing for gem5
-
-The gem5 "MultiSim" module allows for multiple simulations to be run from a single gem5 execution via a single gem5 configuration script.
-This allows for multiple simulations to be run in parallel in a structured manner.
-
-To use MultiSim first create multiple simulators and add them to the MultiSim with the `add_simulator` function.
-If needed, limit the maximum number of parallel processes with the `set_num_processes` function.
-Then run the simulations in parallel with the `gem5` binary using  `-m gem5.utils.multisim`.
-
-Here is an example of how to use MultiSim:
-
-```python
-import gem5.utils.multisim as multisim
-
-# Set the maximum number of processes to run in parallel
-multisim.set_num_processes(4)
-
-# Create multiple simulators.
-# In this case, one for each workload in the benchmark suite.
-for workload in benchmark_suite:
-    board = X86Board(
-        # ...
-    )
-    board.set_workload(workload)
-
-    # Useful to set the ID here. This is used to create unique output
-    # directorires for each gem5 process and can be used to idenfify and
-    # run gem5 processes individually.
-    simulator = Simulator(board, id=f"{workload.get_id()}")
-    multisim.add_simulator(simulator)
-```
-
-Then to run the simulations in parallel:
-
-```sh
-<gem5 binary> -m gem5.utils.multisim <config script>
-```
-
-The output directory ("m5out" by default) will contain sub-directories for each simulation run.
-The sub-directory will be named after the simulator ID set in the configuration script.
-We therefore recommend setting the simulator ID to something meaningful to help identify the output directories (i.e., the workload run or something identifying the meaningful characteristics of the simulated system in comparison to others).
-
-If only one simulation specified in the config needs run, you can do so with:
-
-```sh
-<gem5 binary>  <config script> --list # Lists the simulations by ID
-
-<gem5 binary> <config script> <ID> # Run the simulation with the specified ID.
-```
-
-Example scripts of using MultiSim can be found in "configs/example/gem5_library/multisim".
-
-### RISC-V Vector Extension Support
-
-There have been significant improvements to the RVV support in gem5 including
-
-* Fixed viota (#1137)
-* Fixed vrgather (#1134)
-* Added RVV FP16 support (#1123)
-* Fixed widening and narrowing instructions (#1079)
-* Fixed bug in vfmv.f.s (#863)
-* Add unit stride segment loads and stores (#851) (#913)
-* Fix vl in masked load/store (#830)
-* Add unit-stride loads (#794)
-* Fix many RVV instructions (#814) (#805) (#715)
-
-### General RISC-V bugfixes
-
-* Fixed problem in TLB lookup (#1264)
-* Fixed sign-extended branch target (#1173)
-* Fixed compressed jump instructions (#1163)
-* Fixed GDB connection (#1152)
-* Fixed CSR behavior (#1099)
-* Add Integer conditional operations Zicond (#1078)
-* Add RISC-V Semihosting support (#681)
-* Added more detailed instruction types (#589)
-* Fixed 32-bit m5op arguments (#900)
-* Fixed c.fswsp and c.fsw (#998) (#1005)
-* Update PLIC implementation (#886)
-* Fix fflags behavior in O3 (#868)
-* Add support for local interrupts (#813)
-* Removebit 63 of physical address (#756)
-
-## Improvements
-
-* Added an new generator which can generate requests based on [spatter](https://github.com/hpcgarage/spatter) patterns.
-* KVM is now supported in the gem5 Standard Library ARM Board.
-* Generic Cache template added to the Standard Library (#745)
-* Support added for partitioning caches.
-* The Standard Library `obtain_resources` function can request multiple resources at once thus reducing delay associated with multiple requests.
-* An official gem5 DevContainer has been added to the gem5 repository.
-This can be used to build and run gem5 in consistent environment and enables GitHub Codespaces support.
-
-### gem5 Python Statistics
-
-The gem5 Python statistics API has been improved.
-The gem5 Project's general intent with this improvement is make it easier and more desirable to obtain and interact with gem5 simulation statistics via Python.
-
-For example, the following code snippet demonstrates how to obtain statistics from a gem5 simulation:
-
-```python
-from m5.stats.gem5stats import get_simstat
-
-## Setup and run the configuation ...
-simstat = get_simstat(board)
-
-# Print the number of cycles the CPU at index 0 has executed.
-print(simstat.cpu[0].numCycles)
-
-# Strings can also be used to access statistics.
-print(simstat['cpu'][0]['numCycles'])
-
-# Print the total number of cycles executed by all CPUs.
-print(sum(simstat.cpu[i].numCycles for i in range(len(simstat.cpu))))
-```
-
-We hope the usage of the gem5 Python statistics API will be more intuitive and easier to use while allowing better processing of statistical data.
-
-### GPU Model
-
-* Support for MI300X and MI200 GPU models including their features and most instructions.
-* ROCm 6.1 disk image and compile docker files have been added. ROCm 5.4.2 and 4.2 resources are removed.
-* The deprecated GCN3 ISA has been removed. Use VEGA instead.
-
-## Bug Fixes
-
-* An integer overflow error known to affect the `AddrRange` class has been fixed.
-* Fix fflags behavior of floating point instruction in RISC-V for Out-of-Order CPUs.
-
-### Arm FEAT_MPAM Support
-
-An initial implementation of FEAT_MPAM has been introduced in gem5 with the capability to statically partition
-classic caches. Guidance on how to use this is available on a Arm community [blog post](https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/gem5-cache-partitioning)
-
-# Version 23.1
-
-gem5 Version 23.1 is our first release where the development has been on GitHub.
-During this release, there have been 362 pull requests merged which comprise 416 commits with 51 unique contributors.
-
-## Significant API and user-facing changes
-
-### The gem5 build can is now configured with `kconfig`
-
-* Most gem5 builds without customized options (excluding double dash options) (e.g. , build/X86/gem5.opt) are backwards compatible and require no changes to your current workflows.
-* All of the default builds in `build_opts` are unchanged and still available.
-* However, if you want to specialize your build. For example, use customized ruby protocol. The command `scons PROTOCOL=<PROTOCAL_NAME> build/ALL/gem5.opt` will not work anymore. you now have to use `scons <kconfig command>` to update the ruby protocol as example. The double dash options (`--without-tcmalloc`, `--with-asan` and so on) are still continue to work as normal.
-* For more details refer to the documentation here: [kconfig documentation](https://www.gem5.org/documentation/general_docs/kconfig_build_system/)
-
-### Standard library improvements
-
-#### `WorkloadResource` added to resource specialization
-
-* The `Workload` and `CustomWorkload` classes are now deprecated. They have been transformed into wrappers for the `obtain_resource` and `WorkloadResource` classes in `resource.py`, respectively.
-* Code utilizing the older API will continue to function as expected but will trigger a warning message. To update code using the `Workload` class, change the call from `Workload(id='resource_id', resource_version='1.0.0')` to `obtain_resource(id='resource_id', resource_version='1.0.0')`. Similarly, to update code using the `CustomWorkload` class, change the call from `CustomWorkload(function=func, parameters=params)` to `WorkloadResource(function=func, parameters=params)`.
-* Workload resources in gem5 can now be directly acquired using the `obtain_resource` function, just like other resources.
-
-#### Introducing Suites
-
-Suites is a new category of resource being introduced in gem5. Documentation of suites can be found here: [suite documentation](https://www.gem5.org/documentation/gem5-stdlib/suites).
-
-#### Other API changes
-
-* All resource object now have their own `id` and `category`. Each resource class has its own `__str__()` function which return its information in the form of **category(id, version)** like **BinaryResource(id='riscv-hello', resource_version='1.0.0')**.
-* Users can use GEM5_RESOURCE_JSON  and GEM5_RESOURCE_JSON_APPEND env variables to overwrite all the data sources with the provided JSON and append a JSON file to all the data source respectively. More information can be found [here](https://www.gem5.org/documentation/gem5-stdlib/using-local-resources).
-
-### Other user-facing changes
-
-* Added support for clang 15 and clang 16
-* gem5 no longer supports building on Ubuntu 18.04
-* GCC 7, GCC 9, and clang 6 are no longer supported
-* Two `DRAMInterface` stats have changed names (`bytesRead` and `bytesWritten`). For instance, `board.memory.mem_ctrl.dram.bytesRead` and `board.memory.mem_ctrl.dram.bytesWritten`. These are changed to `dramBytesRead` and `dramBytesWritten` so they don't collide with the stat with the same name in `AbstractMemory`.
-* The stats for `NVMInterface` (`bytesRead` and `bytesWritten`) have been change to `nvmBytesRead` and `nvmBytesWritten` as well.
-
-## Full-system GPU model improvements
-
-* Support for up to latest ROCm 5.7.1.
-* Various changes to enable PyTorch/TensorFlow simulations.
-* New packer disk image script containing ROCm 5.4.2, PyTorch 2.0.1, and Tensorflow 2.11.
-* GPU instructions can now perform atomics on host addresses.
-* The provided configs scripts can now run KVM on more restrictive setups.
-* Add support to checkpoint and restore between kernels in GPUFS, including adding various AQL, HSA Queue, VMID map, MQD attributes, GART translations, and PM4Queues to GPU checkpoints
-* move GPU cache recorder code to RubyPort instead of Sequencer/GPUCoalescer to allow checkpointing to occur
-* add support for flushing GPU caches, as well as cache cooldown/warmup support, for checkpoints
-* Update vega10_kvm.py to add checkpointing instructions
-
-## SE mode GPU model improvements
-
-* started adding support for mmap'ing inputs for GPUSE tests, which reduces their runtime by 8-15% per run
-
-## GPU model improvements
-
-* update GPU VIPER and Coalescer support to ensure correct replacement policy behavior when multiple requests from the same CU are concurrently accessing the same line
-* fix bug with GPU VIPER to resolve a race conflict for loads that bypass the TCP (L1D$)
-* fix bug with MRU replacement policy updates in GPU SQC (I$)
-* update GPU and Ruby debug prints to resolve various small errors
-* Add configurable GPU L1,L2 num banks and L2 latencies
-* Add decodings for new MI100 VOP2 insts
-* Add GPU GLC Atomic Resource Constraints to better model how atomic resources are shared at GPU TCC (L2$)
-* Update GPU tester to work with both requests that bypass all caches (SLC) and requests that bypass only the TCP (L1D$)
-* Fixes for how write mask works for GPU WB L2 caches
-* Added support for WB and WT GPU atomics
-* Added configurable support to better model the latency of GPU atomic requests
-* fix GPU's default number of HW barrier/CU to better model amount of concurrency GPU CUs should have
-
-## RISC-V RVV 1.0 implemented
-
-This was a huge undertaking by a large number of people!
-Some of these people include Adrià Armejach who pushed it over the finish line, Xuan Hu who pushed the most recent version to gerrit that Adrià picked up,
-Jerin Joy who did much of the initial work, and many others who contributed to the implementation including Roger Chang, Hoa Nguyen who put significant effort into testing and reviewing the code.
-
-* Most of the instructions in the 1.0 spec implemented
-* Works with both FS and SE mode
-* Compatible with Simple CPUs, the O3, and the minor CPU models
-* User can specify the width of the vector units
-* Future improvements
-  * Widening/narrowing instructions are *not* implemented
-  * The model for executing memory instructions is not very high performance
-  * The statistics are not correct for counting vector instruction execution
-
-## ArmISA changes/improvements
-
-* Architectural support for the following extensions:
-  * FEAT_TLBIRANGE
-  * FEAT_FGT
-  * FEAT_TCR2
-  * FEAT_SCTLR2
-
-* Arm support for SVE instructions improved
-* Fixed some FEAT_SEL2 related issues:
-  * [Fix virtual interrupt logic in secure mode](https://github.com/gem5/gem5/pull/584)
-  * [Make interrupt masking handle VHE/SEL2 cases](https://github.com/gem5/gem5/pull/430)
-* Removed support for Arm Jazelle and ThumbEE
-* Implementation of an Arm Capstone Disassembler
-
-## Other notable changes/improvements
-
-* Improvements to the CHI coherence protocol implementation
-* Far atomics implemented in CHI
-* Ruby now supports using the prefetchers from the classic caches, if the protocol supports it. CHI has been extended to support the classic prefetchers.
-* Bug in RISC-V TLB to fixed to correctly count misses and hits
-* Added new [RISC-V Zcb instructions](https://github.com/gem5/gem5/pull/399)
-* RISC-V can now use a separate binary for the bootloader and kernel in FS mode
-* DRAMSys integration updated to latest DRAMSys version (5.0)
-* Improved support for RISC-V privilege modes
-* Fixed bug in switching CPUs with RISC-V
-* CPU branch preditor refactoring to prepare for decoupled front end support
-* Perf is now optional when using the KVM CPU model
-* Improvements to the gem5-SST bridge including updating to SST 13.0
-* Improved formatting of documentation in stdlib
-* By default use isort for python imports in style
-* Many, many testing improvements during the migration to GitHub actions
-* Fixed the elastic trace replaying logic (TraceCPU)
-
-## Known Bugs/Issues
-
-* [RISC-V RVV Bad execution of riscv rvv vss instruction](https://github.com/gem5/gem5/issues/594)
-* [RISC-V Vector Extension float32_t bugs/unsupported widening instructions](https://github.com/gem5/gem5/issues/442)
-* [Implement AVX xsave/xstor to avoid workaround when checkpointing](https://github.com/gem5/gem5/issues/434)
-* [Adding Vector Segmented Loads/Stores to RISC-V V 1.0 implementation](https://github.com/gem5/gem5/issues/382)
-* [Integer overflow in AddrRange subset check](https://github.com/gem5/gem5/issues/240)
-* [RISCV64 TLB refuses to access upper half of physical address space](https://github.com/gem5/gem5/issues/238)
-* [Bug when trying to restore checkpoints in SPARC: “panic: panic condition !pte occurred: Tried to execute unmapped address 0.”](https://github.com/gem5/gem5/issues/197)
-* [BaseCache::recvTimingResp can trigger an assertion error from getTarget() due to MSHR in senderState having no targets](https://github.com/gem5/gem5/issues/100)
-
 # Version 23.0.1.0
 
 This minor release incorporates documentation updates, bug fixes, and some minor improvements.
@@ -586,10 +70,10 @@ Scons no longer defines the `DEBUG` guard in debug builds, so code making using
 
 Also, this release:
 
-* Removes deprecated namespaces. Namespace names were updated a couple of releases ago. This release removes the old names.
-* Uses `MemberEventWrapper` in favor of `EventWrapper` for instance member functions.
-* Adds an extension mechanism to `Packet` and `Request`.
-* Sets x86 CPU vendor string to "HygoneGenuine" to better support GLIBC.
+- Removes deprecated namespaces. Namespace names were updated a couple of releases ago. This release removes the old names.
+- Uses `MemberEventWrapper` in favor of `EventWrapper` for instance member functions.
+- Adds an extension mechanism to `Packet` and `Request`.
+- Sets x86 CPU vendor string to "HygoneGenuine" to better support GLIBC.
 
 ## New features and improvements
 
@@ -621,7 +105,6 @@ Architectural support for Armv9 [Scalable Matrix extension](https://developer.ar
 The implementation employs a simple renaming scheme for the Za array register in the O3 CPU, so that writes to difference tiles in the register are considered a dependency and are therefore serialized.
 
 The following SVE and SIMD & FP extensions have also been implemented:
-
 * FEAT_F64MM
 * FEAT_F32MM
 * FEAT_DOTPROD
@@ -644,31 +127,32 @@ gem5 can now use DRAMSys <https://github.com/tukl-msd/DRAMSys> as a DRAM backend
 
 This release:
 
-* Fully implements RISC-V scalar cryptography extensions.
-* Fully implement RISC-V rv32.
-* Implements PMP lock features.
-* Adds general RISC-V improvements to provide better stability.
+- Fully implements RISC-V scalar cryptography extensions.
+- Fully implement RISC-V rv32.
+- Implements PMP lock features.
+- Adds general RISC-V improvements to provide better stability.
 
 ### Standard library improvements and new components
 
 This release:
 
-* Adds MESI_Three_Level component.
-* Supports ELFies and LoopPoint analysis output from Sniper.
-* Supports DRAMSys in the stdlib.
+- Adds MESI_Three_Level component.
+- Supports ELFies and LoopPoint analysis output from Sniper.
+- Supports DRAMSys in the stdlib.
 
 ## Bugfixes and other small improvements
 
 This release also:
 
-* Removes deprecated python libraries.
-* Adds a DDR5 model.
-* Adds AMD GPU MI200/gfx90a support.
-* Changes building so it no longer "duplicates sources" in build/ which improves support for some IDEs and code analysis. If you still need to duplicate sources you can use the `--duplicate-sources` option to `scons`.
-* Enables `--debug-activate=<object name>` to use debug trace for only a single SimObject (the opposite of `--debug-ignore`). See `--debug-help` for more information.
-* Adds support to exit the simulation loop based on Arm-PMU events.
-* Supports Python 3.11.
-* Adds the idea of a CpuCluster to gem5.
+- Removes deprecated python libraries.
+- Adds a DDR5 model.
+- Adds AMD GPU MI200/gfx90a support.
+- Changes building so it no longer "duplicates sources" in build/ which improves support for some IDEs and code analysis. If you still need to duplicate sources you can use the `--duplicate-sources` option to `scons`.
+- Enables `--debug-activate=<object name>` to use debug trace for only a single SimObject (the opposite of `--debug-ignore`). See `--debug-help` for more information.
+- Adds support to exit the simulation loop based on Arm-PMU events.
+- Supports Python 3.11.
+- Adds the idea of a CpuCluster to gem5.
+
 
 # Version 22.1.0.0
 
@@ -679,23 +163,23 @@ See below for more details!
 
 ## New features and improvements
 
-* The gem5 binary can now be compiled to include multiple ISA targets.
+- The gem5 binary can now be compiled to include multiple ISA targets.
 A compilation of gem5 which includes all gem5 ISAs can be created using: `scons build/ALL/gem5.opt`.
 This will use the Ruby `MESI_Two_Level` cache coherence protocol by default, to use other protocols: `scons build/ALL/gem5.opt PROTOCOL=<other protocol>`.
 The classic cache system may continue to be used regardless as to which Ruby cache coherence protocol is compiled.
-* The `m5` Python module now includes functions to set exit events are particular simululation ticks:
-  * *setMaxTick(tick)* : Used to to specify the maximum simulation tick.
-  * *getMaxTick()* : Used to obtain the maximum simulation tick value.
-  * *getTicksUntilMax()*: Used to get the number of ticks remaining until the maximum tick is reached.
-  * *scheduleTickExitFromCurrent(tick)* : Used to schedule an exit exit event a specified number of ticks in the future.
-  * *scheduleTickExitAbsolute(tick)* : Used to schedule an exit event as a specified tick.
-* We now include the `RiscvMatched` board as part of the gem5 stdlib.
+- The `m5` Python module now includes functions to set exit events are particular simululation ticks:
+    - *setMaxTick(tick)* : Used to to specify the maximum simulation tick.
+    - *getMaxTick()* : Used to obtain the maximum simulation tick value.
+    - *getTicksUntilMax()*: Used to get the number of ticks remaining until the maximum tick is reached.
+    - *scheduleTickExitFromCurrent(tick)* : Used to schedule an exit exit event a specified number of ticks in the future.
+    - *scheduleTickExitAbsolute(tick)* : Used to schedule an exit event as a specified tick.
+- We now include the `RiscvMatched` board as part of the gem5 stdlib.
 This board is modeled after the [HiFive Unmatched board](https://www.sifive.com/boards/hifive-unmatched) and may be used to emulate its behavior.
 See "configs/example/gem5_library/riscv-matched-fs.py" and "configs/example/gem5_library/riscv-matched-hello.py" for examples using this board.
-* An API for [SimPoints](https://doi.org/10.1145/885651.781076) has been added.
+- An API for [SimPoints](https://doi.org/10.1145/885651.781076) has been added.
 SimPoints can substantially improve gem5 Simulation time by only simulating representative parts of a simulation then extrapolating statistical data accordingly.
 Examples of using SimPoints with gem5 can be found in "configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py" and "configs/example/gem5_library/checkpoints/simpoints-se-restore.py".
-* "Workloads" have been introduced to gem5.
+- "Workloads" have been introduced to gem5.
 Workloads have been incorporated into the gem5 Standard library.
 They can be used specify the software to be run on a simulated system that come complete with input parameters and any other dependencies necessary to run a simuation on the target hardware.
 At the level of the gem5 configuration script a user may specify a workload via a board's `set_workload` function.
@@ -703,104 +187,105 @@ For example, `set_workload(Workload("x86-ubuntu-18.04-boot"))` sets the board to
 This workload specifies a boot consisting of the Linux 5.4.49 kernel then booting an Ubunutu 18.04 disk image, to exit upon booting.
 Workloads are agnostic to underlying gem5 design and, via the gem5-resources infrastructure, will automatically retrieve all necessary kernels, disk-images, etc., necessary to execute.
 Examples of using gem5 Workloads can be found in "configs/example/gem5_library/x86-ubuntu-ruby.py" and "configs/example/gem5_library/riscv-ubuntu-run.py".
-* To aid gem5 developers, we have incorporated [pre-commit](https://pre-commit.com) checks into gem5.
+- To aid gem5 developers, we have incorporated [pre-commit](https://pre-commit.com) checks into gem5.
 These checks automatically enforce the gem5 style guide on Python files and a subset of other requirements (such as line length) on altered code prior to a `git commit`.
 Users may install pre-commit by running `./util/pre-commit-install.sh`.
 Passing these checks is a requirement to submit code to gem5 so installation is strongly advised.
-* A multiprocessing module has been added.
+- A multiprocessing module has been added.
 This allows for multiple simulations to be run from a single gem5 execution via a single gem5 configuration script.
 Example of usage found [in this commit message](https://gem5-review.googlesource.com/c/public/gem5/+/63432).
 **Note: This feature is still in development.
 While functional, it'll be subject to subtantial changes in future releases of gem5**.
-* The stdlib's `ArmBoard` now supports Ruby caches.
-* Due to numerious fixes and improvements, Ubuntu 22.04 can be booted as a gem5 workload, both in FS and SE mode.
-* Substantial improvements have been made to gem5's GDB capabilities.
-* The `HBM2Stack` has been added to the gem5 stdlib as a memory component.
-* The `MinorCPU` has been fully incorporated into the gem5 Standard Library.
-* We now allow for full-system simulation of GPU applications.
+- The stdlib's `ArmBoard` now supports Ruby caches.
+- Due to numerious fixes and improvements, Ubuntu 22.04 can be booted as a gem5 workload, both in FS and SE mode.
+- Substantial improvements have been made to gem5's GDB capabilities.
+- The `HBM2Stack` has been added to the gem5 stdlib as a memory component.
+- The `MinorCPU` has been fully incorporated into the gem5 Standard Library.
+- We now allow for full-system simulation of GPU applications.
 The introduction of GPU FS mode allows for the same use-cases as SE mode but reduces the requirement of specific host environments or usage of a Docker container.
 The GPU FS mode also has improved simulated speed by functionally simulating memory copies, and provides an easier update path for gem5 developers.
 An X86 host and KVM are required to run GPU FS mode.
 
 ## API (user facing) changes
 
-* The default CPU Vendor String has been updated to `HygonGenuine`.
+- The default CPU Vendor String has been updated to `HygonGenuine`.
 This is due to newer versions of GLIBC being more strict about checking current system's supported features.
 The previous value, `M5 Simulator`, is not recognized as a valid vendor string and therefore GLIBC returns an error.
-* [The stdlib's `_connect_things` funciton call has been moved from the `AbstractBoard`'s constructor to be run as board pre-instantiation process](https://gem5-review.googlesource.com/c/public/gem5/+/65051).
+- [The stdlib's `_connect_things` funciton call has been moved from the `AbstractBoard`'s constructor to be run as board pre-instantiation process](https://gem5-review.googlesource.com/c/public/gem5/+/65051).
 This is to overcome instances where stdlib components (memory, processor, and cache hierarhcy) require Board information known only after its construction.
 **This change breaks cases where a user utilizes the stdlib `AbstractBoard` but does not use the stdlib `Simulator` module. This can be fixed by adding the `_pre_instantiate` function before `m5.instantiate`**.
 An exception has been added which explains this fix, if this error occurs.
-* The setting of checkpoints has been moved from the stdlib's "set_workload" functions to the `Simulator` module.
+- The setting of checkpoints has been moved from the stdlib's "set_workload" functions to the `Simulator` module.
 Setting of checkpoints via the stdlib's "set_workload" functions is now deprecated and will be removed in future releases of gem5.
-* The gem5 namespace `Trace` has been renamed `trace` to conform to the gem5 style guide.
-* Due to the allowing of multiple ISAs per gem5 build, the `TARGET_ISA`  variable has been replaced with `USE_$(ISA)` variables.
+- The gem5 namespace `Trace` has been renamed `trace` to conform to the gem5 style guide.
+- Due to the allowing of multiple ISAs per gem5 build, the `TARGET_ISA`  variable has been replaced with `USE_$(ISA)` variables.
 For example, if a build contains both the X86 and ARM ISAs the `USE_X86` and `USE_ARM` variables will be set.
 
 ## Big Fixes
 
-* Several compounding bugs were causing bugs with floating point operations within gem5 simulations.
+- Several compounding bugs were causing bugs with floating point operations within gem5 simulations.
 These have been fixed.
-* Certain emulated syscalls were behaving incorrectly when using RISC-V due to incorrect `open(2)` flag values.
+- Certain emulated syscalls were behaving incorrectly when using RISC-V due to incorrect `open(2)` flag values.
 These values have been fixed.
-* The GIVv3 List register mapping has been fixed.
-* Access permissions for GICv3 cpu registers have been fixed.
-* In previous releases of gem5 the `sim_quantum` value was set for all cores when using the Standard Library.
+- The GIVv3 List register mapping has been fixed.
+- Access permissions for GICv3 cpu registers have been fixed.
+- In previous releases of gem5 the `sim_quantum` value was set for all cores when using the Standard Library.
 This caused issues when setting exit events at a particular tick as it resulted in the exit being off by `sim_quantum`.
 As such, the `sim_quantum` value is only when using KVM cores.
-* PCI ranges in `VExpress_GEM5_Foundation` fixed.
-* The `SwitchableProcessor` processor has been fixed to allow switching to a KVM core.
+- PCI ranges in `VExpress_GEM5_Foundation` fixed.
+- The `SwitchableProcessor` processor has been fixed to allow switching to a KVM core.
 Previously the `SwitchableProcessor` only allowed a user to switch from a KVM core to a non-KVM core.
-* The Standard Library has been fixed to permit multicore simulations in SE mode.
-* [A bug was fixed in the rcr X86 instruction](https://gem5.atlassian.net/browse/GEM5-1265).
+- The Standard Library has been fixed to permit multicore simulations in SE mode.
+- [A bug was fixed in the rcr X86 instruction](https://gem5.atlassian.net/browse/GEM5-1265).
 
 ## Build related changes
 
-* gem5 can now be compiled with Scons 4 build system.
-* gem5 can now be compiled with Clang version 14 (minimum Clang version 6).
-* gem5 can now be compiled with GCC Version 12 (minimum GCC version 7).
+- gem5 can now be compiled with Scons 4 build system.
+- gem5 can now be compiled with Clang version 14 (minimum Clang version 6).
+- gem5 can now be compiled with GCC Version 12 (minimum GCC version 7).
+
 
 ## Other minor updates
 
-* The gem5 stdlib examples in "configs/example/gem5_library" have been updated to, where appropriate, use the stdlib's Simulator module.
+- The gem5 stdlib examples in "configs/example/gem5_library" have been updated to, where appropriate, use the stdlib's Simulator module.
 These example configurations can be used for reference as to how `Simulator` module may be utilized in gem5.
-* Granulated SGPR computation has been added for gfx9 gpu-compute.
-* The stdlib statistics have been improved:
-  * A `get_simstats` function has been added to access statistics from the `Simulator` module.
-  * Statistics can be printed: `print(simstats.board.core.some_integer)`.
-* GDB ports are now specified for each workload, as opposed to per-simulation run.
-* The `m5` utility has been expanded to include "workbegin" and "workend" annotations.
+- Granulated SGPR computation has been added for gfx9 gpu-compute.
+- The stdlib statistics have been improved:
+    - A `get_simstats` function has been added to access statistics from the `Simulator` module.
+    - Statistics can be printed: `print(simstats.board.core.some_integer)`.
+- GDB ports are now specified for each workload, as opposed to per-simulation run.
+- The `m5` utility has been expanded to include "workbegin" and "workend" annotations.
 This can be added with `m5 workbegin` and `m5 workend`.
-* A `PrivateL1SharedL2CacheHierarchy` has been added to the Standard Library.
-* A `GEM5_USE_PROXY` environment variable has been added.
+- A `PrivateL1SharedL2CacheHierarchy` has been added to the Standard Library.
+- A `GEM5_USE_PROXY` environment variable has been added.
 This allows users to specify a socks5 proxy server to use when obtaining gem5 resources and the resources.json file.
 It uses the format `<host>:<port>`.
-* The fastmodel support has been improved to function with Linux Kernel 5.x.
-* The `set_se_binary_workload` function now allows for the passing of input parameters to a binary workload.
-* A functional CHI cache hierarchy has been added to the gem5 Standard Library: "src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py".
-* The RISC-V K extension has been added.
+- The fastmodel support has been improved to function with Linux Kernel 5.x.
+- The `set_se_binary_workload` function now allows for the passing of input parameters to a binary workload.
+- A functional CHI cache hierarchy has been added to the gem5 Standard Library: "src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py".
+- The RISC-V K extension has been added.
 It includes the following instructions:
-  * Zbkx: xperm8, xperm4
-  * Zknd: aes64ds, aes64dsm, aes64im, aes64ks1i, aes64ks2
-  * Zkne: aes64es, aes64esm, aes64ks1i, aes64ks2
-  * Zknh: sha256sig0, sha256sig1, sha256sum0, sha256sum1, sha512sig0, sha512sig1, sha512sum0, sha512sum1
-  * Zksed: sm4ed, sm4ks
-  * Zksh: sm3p0, sm3p1
+  - Zbkx: xperm8, xperm4
+  - Zknd: aes64ds, aes64dsm, aes64im, aes64ks1i, aes64ks2
+  - Zkne: aes64es, aes64esm, aes64ks1i, aes64ks2
+  - Zknh: sha256sig0, sha256sig1, sha256sum0, sha256sum1, sha512sig0, sha512sig1, sha512sum0, sha512sum1
+  - Zksed: sm4ed, sm4ks
+  - Zksh: sm3p0, sm3p1
 
 # Version 22.0.0.2
 
 **[HOTFIX]** This hotfix contains a set of critical fixes to be applied to gem5 v22.0.
 This hotfix:
 
-* Fixes the ARM booting of Linux kernels making use of FEAT_PAuth.
-* Removes incorrect `requires` functions in AbstractProcessor and AbstractGeneratorCore.
+- Fixes the ARM booting of Linux kernels making use of FEAT_PAuth.
+- Removes incorrect `requires` functions in AbstractProcessor and AbstractGeneratorCore.
 These `requires` were causing errors when running generators with any ISA other than NULL.
-* Fixes the standard library's `set_se_binary_workload` function to exit on Exit Events (work items) by default.
-* Connects a previously unconnected PCI port in the example SST RISC-V config to the membus.
-* Updates the SST-gem5 README with the correct download links.
-* Adds a `getAddrRanges` function to the `HBMCtrl`.
+- Fixes the standard library's `set_se_binary_workload` function to exit on Exit Events (work items) by default.
+- Connects a previously unconnected PCI port in the example SST RISC-V config to the membus.
+- Updates the SST-gem5 README with the correct download links.
+- Adds a `getAddrRanges` function to the `HBMCtrl`.
 This ensures the XBar connected to the controller can see the address ranges covered by both pseudo channels.
-* Fixes test_download_resources.py so the correct parameter is passed to the download test script.
+- Fixes test_download_resources.py so the correct parameter is passed to the download test script.
 
 # Version 22.0.0.1
 
@@ -821,14 +306,14 @@ See below for more details!
 
 ## New features
 
-* [Arm now models DVM messages for TLBIs and DSBs accurately](https://gem5.atlassian.net/browse/GEM5-1097). This is implemented in the CHI protocol.
-* EL2/EL3 support on by default in ArmSystem
-* HBM controller which supports pseudo channels
-* [Improved Ruby's SimpleNetwork routing](https://gem5.atlassian.net/browse/GEM5-920)
-* Added x86 bare metal workload and better real mode support
-* [Added round-robin arbitration when using multiple prefetchers](https://gem5.atlassian.net/browse/GEM5-1169)
-* [KVM Emulation added for ARM GIGv3](https://gem5.atlassian.net/browse/GEM5-1138)
-* Many improvements to the CHI protocol
+- [Arm now models DVM messages for TLBIs and DSBs accurately](https://gem5.atlassian.net/browse/GEM5-1097). This is implemented in the CHI protocol.
+- EL2/EL3 support on by default in ArmSystem
+- HBM controller which supports pseudo channels
+- [Improved Ruby's SimpleNetwork routing](https://gem5.atlassian.net/browse/GEM5-920)
+- Added x86 bare metal workload and better real mode support
+- [Added round-robin arbitration when using multiple prefetchers](https://gem5.atlassian.net/browse/GEM5-1169)
+- [KVM Emulation added for ARM GIGv3](https://gem5.atlassian.net/browse/GEM5-1138)
+- Many improvements to the CHI protocol
 
 ## Many RISC-V instructions added
 
@@ -877,7 +362,7 @@ An example gem5 configuration script using this board can be found in `configs/e
 
 When the system is configured for NUMA, it has multiple memory ranges, and each memory range is mapped to a corresponding NUMA node. For this, the change enables `createAddrRanges` to map address ranges to only a given HNFs.
 
-Jira ticker [here](https://gem5.atlassian.net/browse/GEM5-1187).
+Jira ticker here: https://gem5.atlassian.net/browse/GEM5-1187.
 
 ## API (user-facing) changes
 
@@ -885,7 +370,7 @@ Jira ticker [here](https://gem5.atlassian.net/browse/GEM5-1187).
 
 For instance, the `O3CPU` is now the `X86O3CPU` and `ArmO3CPU`, etc.
 This requires a number of changes if you have your own CPU models.
-See [here](https://gem5-review.googlesource.com/c/public/gem5/+/52490) for details.
+See https://gem5-review.googlesource.com/c/public/gem5/+/52490 for details.
 
 Additionally, this requires changes in any configuration script which inherits from the old CPU types.
 
@@ -899,31 +384,31 @@ Now, if you want to compile a CPU model for a particular ISA you will have to ad
 
 If you have any specialized CPU models or any ISAs which are not in the mainline, expect many changes when rebasing on this release.
 
-* No longer use read/setIntReg (e.g., see [link](https://gem5-review.googlesource.com/c/public/gem5/+/49766))
-* InvalidRegClass has changed (e.g., see [link](https://gem5-review.googlesource.com/c/public/gem5/+/49745))
-* All of the register classes have changed (e.g., see [link](https://gem5-review.googlesource.com/c/public/gem5/+/49764/))
-* `initiateSpecialMemCmd` renamed to `initiateMemMgmtCmd` to generalize to other command beyond HTM (e.g., DVM/TLBI)
-* `OperandDesc` class added (e.g., see [link](https://gem5-review.googlesource.com/c/public/gem5/+/49731))
-* Many cases of `TheISA` have been removed
+- No longer use read/setIntReg (e.g., see https://gem5-review.googlesource.com/c/public/gem5/+/49766)
+- InvalidRegClass has changed (e.g., see https://gem5-review.googlesource.com/c/public/gem5/+/49745)
+- All of the register classes have changed (e.g., see https://gem5-review.googlesource.com/c/public/gem5/+/49764/)
+- `initiateSpecialMemCmd` renamed to `initiateMemMgmtCmd` to generalize to other command beyond HTM (e.g., DVM/TLBI)
+- `OperandDesc` class added (e.g., see https://gem5-review.googlesource.com/c/public/gem5/+/49731)
+- Many cases of `TheISA` have been removed
 
 ## Bug Fixes
 
-* [Fixed RISC-V call/ret instruction decoding](https://gem5-review.googlesource.com/c/public/gem5/+/58209). The fix adds IsReturn` and `IsCall` flags for RISC-V jump instructions by defining a new `JumpConstructor` in "standard.isa". Jira Ticket [here](https://gem5.atlassian.net/browse/GEM5-1139).
-* [Fixed x86 Read-Modify-Write behavior in multiple timing cores with classic caches](https://gem5-review.googlesource.com/c/public/gem5/+/55744). Jira Ticket [here](https://gem5.atlassian.net/browse/GEM5-1105).
-* [The circular buffer for the O3 LSQ has been fixed](https://gem5-review.googlesource.com/c/public/gem5/+/58649). This issue affected running the O3 CPU with large workloaders. Jira Ticket [here](https://gem5.atlassian.net/browse/GEM5-1203).
-* [Removed "memory-leak"-like error in RISC-V lr/sc implementation](https://gem5-review.googlesource.com/c/public/gem5/+/55663). Jira issue [here](https://gem5.atlassian.net/browse/GEM5-1170).
-* [Resolved issues with Ruby's memtest](https://gem5-review.googlesource.com/c/public/gem5/+/56811). In gem5 v21.2, If the size of the address range was smaller than the maximum number of outstandnig requests allowed downstream, the tester would get stuck trying to find a unique address. This has been resolved.
+- [Fixed RISC-V call/ret instruction decoding](https://gem5-review.googlesource.com/c/public/gem5/+/58209). The fix adds IsReturn` and `IsCall` flags for RISC-V jump instructions by defining a new `JumpConstructor` in "standard.isa". Jira Ticket here: https://gem5.atlassian.net/browse/GEM5-1139.
+- [Fixed x86 Read-Modify-Write behavior in multiple timing cores with classic caches](https://gem5-review.googlesource.com/c/public/gem5/+/55744). Jira Ticket here: https://gem5.atlassian.net/browse/GEM5-1105.
+- [The circular buffer for the O3 LSQ has been fixed](https://gem5-review.googlesource.com/c/public/gem5/+/58649). This issue affected running the O3 CPU with large workloaders. Jira Ticket here: https://gem5.atlassian.net/browse/GEM5-1203.
+- [Removed "memory-leak"-like error in RISC-V lr/sc implementation](https://gem5-review.googlesource.com/c/public/gem5/+/55663). Jira issue here: https://gem5.atlassian.net/browse/GEM5-1170.
+- [Resolved issues with Ruby's memtest](https://gem5-review.googlesource.com/c/public/gem5/+/56811). In gem5 v21.2, If the size of the address range was smaller than the maximum number of outstandnig requests allowed downstream, the tester would get stuck trying to find a unique address. This has been resolved.
 
 ## Build-related changes
 
-* Variable in `env` in the SConscript files now requires you to use `env['CONF']` to access them. Anywhere that `env['<VARIABLE>']` appeared should noe be `env['CONF']['<VARIABLE>']`
-* Internal build files are now in a per-target `gem5.build` directory
-* All build variable are per-target and there are no longer any shared variables.
+- Variable in `env` in the SConscript files now requires you to use `env['CONF']` to access them. Anywhere that `env['<VARIABLE>']` appeared should noe be `env['CONF']['<VARIABLE>']`
+- Internal build files are now in a per-target `gem5.build` directory
+- All build variable are per-target and there are no longer any shared variables.
 
 ## Other changes
 
-* New bootloader is required for Arm VExpress_GEM5_Foundation platform. See [here](https://gem5.atlassian.net/browse/GEM5-1222) for details.
-* The MemCtrl interface has been updated to use more inheritance to make extending it to other memory types (e.g., HBM pseudo channels) easier.
+- New bootloader is required for Arm VExpress_GEM5_Foundation platform. See https://gem5.atlassian.net/browse/GEM5-1222 for details.
+- The MemCtrl interface has been updated to use more inheritance to make extending it to other memory types (e.g., HBM pseudo channels) easier.
 
 # Version 21.2.1.1
 
@@ -961,28 +446,28 @@ This has now been wrapped in a larger "standard library".
 
 The *gem5 standard library* is a Python package which contains the following:
 
-* **Components:** A set of Python classes which wrap gem5's models. Some of the components are preconfigured to match real hardware (e.g., `SingleChannelDDR3_1600`) and others are parameterized. Components can be combined together onto *boards* which can be simulated.
-* **Resources:** A set of utilities to interact with the gem5-resources repository/website. Using this module allows you to *automatically* download and use many of gem5's prebuilt resources (e.g., kernels, disk images, etc.).
-* **Simulate:** *THIS MODULE IS IN BETA!* A simpler interface to gem5's simulation/run capabilities. Expect API changes to this module in future releases. Feedback is appreciated.
-* **Prebuilt**: These are fully functioning prebuilt systems. These systems are built from the components in `components`. This release has a "demo" board to show an example of how to use the prebuilt systems.
+- **Components:** A set of Python classes which wrap gem5's models. Some of the components are preconfigured to match real hardware (e.g., `SingleChannelDDR3_1600`) and others are parameterized. Components can be combined together onto *boards* which can be simulated.
+- **Resources:** A set of utilities to interact with the gem5-resources repository/website. Using this module allows you to *automatically* download and use many of gem5's prebuilt resources (e.g., kernels, disk images, etc.).
+- **Simulate:** *THIS MODULE IS IN BETA!* A simpler interface to gem5's simulation/run capabilities. Expect API changes to this module in future releases. Feedback is appreciated.
+- **Prebuilt**: These are fully functioning prebuilt systems. These systems are built from the components in `components`. This release has a "demo" board to show an example of how to use the prebuilt systems.
 
 Examples of using the gem5 standard library can be found in `configs/example/gem5_library/`.
 The source code is found under `src/python/gem5`.
 
 ## Many Arm improvements
 
-* [Improved configurability for Arm architectural extensions](https://gem5.atlassian.net/browse/GEM5-1132): we have improved how to enable/disable architectural extensions for an Arm system. Rather than working with indipendent boolean values, we now use a unified ArmRelease object modelling the architectural features supported by a FS/SE Arm simulation
-* [Arm TLB can store partial entries](https://gem5.atlassian.net/browse/GEM5-1108): It is now possible to configure an ArmTLB as a walk cache: storing intermediate PAs obtained during a translation table walk.
-* [Implemented a multilevel TLB hierarchy](https://gem5.atlassian.net/browse/GEM5-790): enabling users to compose/model a customizable multilevel TLB hierarchy in gem5. The default Arm MMU has now an Instruction L1 TLB, a Data L1 TLB and a Unified (Instruction + Data) L2 TLB.
-* Provided an Arm example script for the gem5-SST integration (<https://gem5.atlassian.net/browse/GEM5-1121>).
+- [Improved configurability for Arm architectural extensions](https://gem5.atlassian.net/browse/GEM5-1132): we have improved how to enable/disable architectural extensions for an Arm system. Rather than working with indipendent boolean values, we now use a unified ArmRelease object modelling the architectural features supported by a FS/SE Arm simulation
+- [Arm TLB can store partial entries](https://gem5.atlassian.net/browse/GEM5-1108): It is now possible to configure an ArmTLB as a walk cache: storing intermediate PAs obtained during a translation table walk.
+- [Implemented a multilevel TLB hierarchy](https://gem5.atlassian.net/browse/GEM5-790): enabling users to compose/model a customizable multilevel TLB hierarchy in gem5. The default Arm MMU has now an Instruction L1 TLB, a Data L1 TLB and a Unified (Instruction + Data) L2 TLB.
+- Provided an Arm example script for the gem5-SST integration (<https://gem5.atlassian.net/browse/GEM5-1121>).
 
 ## GPU improvements
 
-* Vega support: gfx900 (Vega) discrete GPUs are now both supported and tested with [gem5-resources applications](https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/gpu/).
-* Improvements to the VIPER coherence protocol to fix bugs and improve performance: this improves scalability for large applications running on relatively small GPU configurations, which caused deadlocks in VIPER's L2.  Instead of continually replaying these requests, the updated protocol instead wakes up the pending requests once the prior request to this cache line has completed.
-* Additional GPU applications: The [Pannotia graph analytics benchmark suite](https://github.com/pannotia/pannotia) has been added to gem5-resources, including Makefiles, READMEs, and sample commands on how to run each application in gem5.
-* Regression Testing: Several GPU applications are now tested as part of the nightly and weekly regressions, which improves test coverage and avoids introducing inadvertent bugs.
-* Minor updates to the architecture model: We also added several small changes/fixes to the HSA queue size (to allow larger GPU applications with many kernels to run), the TLB (to create GCN3- and Vega-specific TLBs), adding new instructions that were previously unimplemented in GCN3 and Vega, and fixing corner cases for some instructions that were leading to incorrect behavior.
+- Vega support: gfx900 (Vega) discrete GPUs are now both supported and tested with [gem5-resources applications](https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/gpu/).
+- Improvements to the VIPER coherence protocol to fix bugs and improve performance: this improves scalability for large applications running on relatively small GPU configurations, which caused deadlocks in VIPER's L2.  Instead of continually replaying these requests, the updated protocol instead wakes up the pending requests once the prior request to this cache line has completed.
+- Additional GPU applications: The [Pannotia graph analytics benchmark suite](https://github.com/pannotia/pannotia) has been added to gem5-resources, including Makefiles, READMEs, and sample commands on how to run each application in gem5.
+- Regression Testing: Several GPU applications are now tested as part of the nightly and weekly regressions, which improves test coverage and avoids introducing inadvertent bugs.
+- Minor updates to the architecture model: We also added several small changes/fixes to the HSA queue size (to allow larger GPU applications with many kernels to run), the TLB (to create GCN3- and Vega-specific TLBs), adding new instructions that were previously unimplemented in GCN3 and Vega, and fixing corner cases for some instructions that were leading to incorrect behavior.
 
 ## gem5-SST bridges revived
 
@@ -1003,13 +488,13 @@ However, they should be simple to extend to other ISAs through small source chan
 
 ## Other improvements
 
-* Removed master/slave terminology: this was a closed ticket which was marked as done even though there were multiple references of master/slave in the config scripts which we fixed.
-* Armv8.2-A FEAT_UAO implementation.
-* Implemented 'at' variants of file syscall in SE mode (<https://gem5.atlassian.net/browse/GEM5-1098>).
-* Improved modularity in SConscripts.
-* Arm atomic support in the CHI protocol
-* Many testing improvements.
-* New "tester" CPU which mimics GUPS.
+- Removed master/slave terminology: this was a closed ticket which was marked as done even though there were multiple references of master/slave in the config scripts which we fixed.
+- Armv8.2-A FEAT_UAO implementation.
+- Implemented 'at' variants of file syscall in SE mode (<https://gem5.atlassian.net/browse/GEM5-1098>).
+- Improved modularity in SConscripts.
+- Arm atomic support in the CHI protocol
+- Many testing improvements.
+- New "tester" CPU which mimics GUPS.
 
 # Version 21.1.0.2
 
@@ -1024,7 +509,7 @@ This hotfix initializes using loops which fixes the broken statistics.
 # Version 21.1.0.0
 
 Since v21.0 we have received 780 commits with 48 unique contributors, closing 64 issues on our [Jira Issue Tracker](https://gem5.atlassian.net/).
-In addition to our first gem5 minor release, we have included a range of new features, and API changes which we outline below.
+In addition to our [first gem5 minor release](#version-21.0.1.0), we have included a range of new features, and API changes which we outline below.
 
 ## Added the Components Library [Alpha Release]
 
@@ -1083,7 +568,7 @@ Classes that handle set dueling have been created ([Dueler and DuelingMonitor](h
 They can be used in conjunction with different cache policies.
 A [replacement policy that uses it](https://gem5.googlesource.com/public/gem5/+/refs/tags/v21.1.0.0/src/mem/cache/replacement_policies/dueling_rp.hh) has been added for guidance.
 
-## RISC-V is now supported as a host machine
+## RISC-V is now supported as a host machine.
 
 gem5 is now compilable and runnable on a RISC-V host system.
 
@@ -1093,7 +578,6 @@ Deprecation MACROS have been added for deprecating namespaces (`GEM5_DEPRECATED_
 
 **Note:**
 For technical reasons, using old macros won't produce any deprecation warnings.
-
 ## Refactoring of the gem5 Namespaces
 
 Snake case has been adopted as the new convention for name spaces.
@@ -1172,9 +656,9 @@ Version 21.0.1 is a minor gem5 release consisting of bug fixes. The 21.0.1 relea
 * Fixes the [GCN-GPU Dockerfile](https://gem5.googlesource.com/public/gem5/+/refs/tags/v21.0.1.0/util/dockerfiles/gcn-gpu/Dockerfile) to pull from the v21-0 bucket.
 * Fixes the tests to download from the v21-0 bucket instead of the develop bucket.
 * Fixes the Temperature class:
-  * Fixes [fs_power.py](https://gem5.googlesource.com/public/gem5/+/refs/tags/v21.0.1.0/configs/example/arm/fs_power.py), which was producing a ["Temperature is not JSON serializable" error](https://gem5.atlassian.net/browse/GEM5-951).
-  * Fixes temperature printing in `config.ini`.
-  * Fixes the pybind export for the `from_kelvin` function.
+    * Fixes [fs_power.py](https://gem5.googlesource.com/public/gem5/+/refs/tags/v21.0.1.0/configs/example/arm/fs_power.py), which was producing a ["Temperature is not JSON serializable" error](https://gem5.atlassian.net/browse/GEM5-951).
+    * Fixes temperature printing in `config.ini`.
+    * Fixes the pybind export for the `from_kelvin` function.
 * Eliminates a duplicated name warning in [ClockTick](https://gem5.googlesource.com/public/gem5/+/refs/tags/v21.0.1.0/src/systemc/channel/sc_clock.cc).
 * Fixes the [Ubuntu 18.04 Dockerfile](https://gem5.googlesource.com/public/gem5/+/refs/tags/v21.0.1.0/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile) to use Python3 instead of Python2.
 * Makes [verify.py](https://gem5.googlesource.com/public/gem5/+/refs/tags/v21.0.1.0/src/systemc/tests/verify.py) compatible with Python3.
@@ -1285,7 +769,7 @@ This bug affected the overall behavior of the Garnet Network Model.
 # Version 20.1.0.0
 
 Thank you to everyone that made this release possible!
-This has been a very productive release with [150 issues](https://gem5.atlassian.net/), over 650 commits (a 25% increase from the 20.0 release), and 58 unique contributors (a 100% increase!).
+This has been a very productive release with [150 issues](https://gem5.atlassian.net/), over 650  commits (a 25% increase from the 20.0 release), and 58 unique contributors (a 100% increase!).
 
 ## Process changes
 
@@ -1369,7 +853,7 @@ See <http://www.gem5.org/documentation/general_docs/building> for gem5's current
 * There may be some bugs introduced with this change as there were many places in the Python configurations which relied on "duck typing".
 * This change is mostly backwards compatible and warning will be issued until at least gem5-20.2.
 
-```txt
+```
 MasterPort -> RequestorPort
 SlavePort -> ResponsePort
 
@@ -1443,7 +927,7 @@ Below are some of the highlights, though I'm sure I've missed some important cha
   * All full system config/run scripts must be updated (e.g., anything that used the `LinuxX86System` or similar SimObject).
   * Many of the parameters of `System` are now parameters of the `Workload` (see `src/sim/Workload.py`).
     * For instance, many parameters of `LinuxX86System` are now part of `X86FsLinux` which is now the `workload` parameter of the `System` SimObject.
-  * See [here](https://gem5-review.googlesource.com/c/public/gem5/+/24283/) and [here](https://gem5-review.googlesource.com/c/public/gem5/+/26466) for more details.
+  * See https://gem5-review.googlesource.com/c/public/gem5/+/24283/ and https://gem5-review.googlesource.com/c/public/gem5/+/26466 for more details.
 * Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V.
   * (Some) Baremetal OSes are now supported.
 * Improvements to DRAM model:

SConsopts

@@ -1,6 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2024 ARM Limited
+# Copyright (c) 2013, 2015-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -12,6 +10,11 @@
 # unmodified and in its entirety in all distributions of the software,
 # modified or unmodified, in source code or in binary form.
 #
+# Copyright (c) 2011 Advanced Micro Devices, Inc.
+# Copyright (c) 2009 The Hewlett-Packard Development Company
+# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
 # met: redistributions of source code must retain the above copyright
@@ -35,18 +38,16 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import os
+import os.path
+
+from gem5_scons import warning
+
 Import('*')
 
-SimObject('PartitioningPolicies.py', sim_objects=[
-    'PartitionManager',
-    'BasePartitioningPolicy',
-    'MaxCapacityPartitioningPolicy',
-    'WayPolicyAllocation',
-    'WayPartitioningPolicy']
+sticky_vars.AddVariables(
+    ('BATCH', 'Use batch pool for build and tests', False),
+    ('BATCH_CMD', 'Batch pool submission command name', 'qdo'),
+    ('M5_BUILD_CACHE', 'Cache built objects in this directory', False),
+    ('USE_EFENCE', 'Link with Electric Fence malloc debugger', False),
     )
-
-Source('base_pp.cc')
-Source('max_capacity_pp.cc')
-Source('way_allocation.cc')
-Source('way_pp.cc')
-Source('partition_manager.cc')

SConstruct

@@ -44,6 +44,15 @@
 #
 # SCons top-level build description (SConstruct) file.
 #
+# While in this directory ('gem5'), just type 'scons' to build the default
+# configuration (see below), or type 'scons build/<CONFIG>/<binary>'
+# to build some other configuration (e.g., 'build/X86/gem5.opt' for
+# the optimized X86 version).
+#
+# You can build gem5 in a different directory as long as there is a
+# 'build/<CONFIG>' somewhere along the target path.  The build system
+# expects that all configs under the same build directory are being
+# built for the same host system.
 #
 # Examples:
 #
@@ -68,11 +77,10 @@
 
 # Global Python imports
 import atexit
-import itertools
 import os
 import sys
 
-from os import mkdir, remove, environ, listdir
+from os import mkdir, remove, environ
 from os.path import abspath, dirname, expanduser
 from os.path import isdir, isfile
 from os.path import join, split
@@ -107,6 +115,8 @@ AddOption('--no-colors', dest='use_colors', action='store_false',
           help="Don't add color to abbreviated scons output")
 AddOption('--with-cxx-config', action='store_true',
           help="Build with support for C++-based configuration")
+AddOption('--default',
+          help='Override which build_opts file to use for defaults')
 AddOption('--ignore-style', action='store_true',
           help='Disable style checking hooks')
 AddOption('--linker', action='store', default=None, choices=linker_options,
@@ -117,8 +127,6 @@ AddOption('--no-compress-debug', action='store_true',
           help="Don't compress debug info in build files")
 AddOption('--with-lto', action='store_true',
           help='Enable Link-Time Optimization')
-AddOption('--with-libcxx', action='store_true',
-          help='Use libc++ as the C++ standard library (requires Clang)')
 AddOption('--verbose', action='store_true',
           help='Print full tool command lines')
 AddOption('--without-python', action='store_true',
@@ -133,8 +141,6 @@ AddOption('--with-systemc-tests', action='store_true',
           help='Build systemc tests')
 AddOption('--install-hooks', action='store_true',
           help='Install revision control hooks non-interactively')
-AddOption('--limit-ld-memory-usage', action='store_true',
-          help='Tell ld, the linker, to reduce memory usage.')
 AddOption('--gprof', action='store_true',
           help='Enable support for the gprof profiler')
 AddOption('--pprof', action='store_true',
@@ -156,7 +162,6 @@ sys.path[1:1] = [ Dir('#build_tools').abspath ]
 # declared above.
 from gem5_scons import error, warning, summarize_warnings, parse_build_path
 from gem5_scons import TempFileSpawn, EnvDefaults, MakeAction, MakeActionTool
-from gem5_scons import kconfig
 import gem5_scons
 from gem5_scons.builders import ConfigFile, AddLocalRPATH, SwitchingHeaders
 from gem5_scons.builders import Blob
@@ -200,71 +205,7 @@ if not ('CC' in main and 'CXX' in main):
     error("No C++ compiler installed (package g++ on Ubuntu and RedHat)")
 
 # Find default configuration & binary.
-default_target = environ.get('M5_DEFAULT_BINARY', None)
-if default_target:
-    Default(default_target)
-
-# If no target is set, even a default, print help instead.
-if not BUILD_TARGETS:
-    warning("No target specified, and no default.")
-    SetOption('help', True)
-
-buildopts_dir = Dir('#build_opts')
-buildopts = list([f for f in os.listdir(buildopts_dir.abspath) if
-        isfile(os.path.join(buildopts_dir.abspath, f))])
-buildopts.sort()
-
-buildopt_list = '\n'.join(' ' * 10 + buildopt for buildopt in buildopts)
-
-Help(f"""
-Targets:
-        To build gem5 using a predefined configuration, use a target with
-        a directory called "build" in the path, followed by a directory named
-        after a predefined configuration in "build_opts" directory, and then
-        the actual target, likely a gem5 binary. For example:
-
-        scons build/ALL/gem5.opt
-
-        The "build" component tells SCons that the next part names an initial
-        configuration, and the part after that is the actual target.
-        The predefined targets currently available are:
-
-{buildopt_list}
-
-        The extension on the gem5 binary specifies what type of binary to
-        build. Options are:
-
-        debug: A debug binary with optimizations turned off and debug info
-            turned on.
-        opt: An optimized binary with debugging still turned on.
-        fast: An optimized binary with debugging, asserts, and tracing
-            disabled.
-
-        gem5 can also be built as a static or dynamic library. In that case,
-        the extension is determined by the operating system, so the binary type
-        is part of the target file name. For example:
-
-        scons build/ARM/libgem5_opt.so
-
-        In MacOS, the extension should change to "dylib" like this:
-
-        scons build/ARM/libgem5_opt.dylib
-
-        To build unit tests, you can use a target like this:
-
-        scons build/RISCV/unittests.debug
-
-        The unittests.debug part of the target is actual a directory which
-        holds the results for all the unit tests built with the "debug"
-        settings. When that's used as the target, SCons will build all the
-        files under that directory, which will run all the tests.
-
-        To build and run an individual test, you can built it's binary
-        specifically and then run it manually:
-
-        scons build/SPARC/base/bitunion.test.opt
-        build/SPARC/base/bitunion.test.opt
-""", append=True)
+Default(environ.get('M5_DEFAULT_BINARY', 'build/ARM/gem5.debug'))
 
 
 ########################################################################
@@ -274,134 +215,52 @@ Targets:
 #
 ########################################################################
 
-kconfig_actions = (
-    'defconfig',
-    'guiconfig',
-    'listnewconfig',
-    'menuconfig',
-    'oldconfig',
-    'olddefconfig',
-    'savedefconfig',
-    'setconfig',
-)
-
-Help("""
-Kconfig:
-        In addition to the default configs, you can also create your own
-        configs, or edit one that already exists. To use one of the kconfig
-        tools with a particular directory, use a target which is the directory
-        to configure, and then the name of the tool. For example, to run
-        menuconfig on directory build_foo/bar, run:
-
-        scons menuconfig build_foo/bar
-
-        will set up a build directory in build_foo/bar if one doesn't already
-        exist, and open the menuconfig editor to view/set configuration
-        values.
-
-Kconfig tools:
-        defconfig:
-        Set up a config using values specified in a defconfig file, or if no
-        value is given, use the default. The second argument specifies the
-        defconfig file. A defconfig file in the build_opts directory can be
-        implicitly specified in the build path via `build/<defconfig file>/`
-
-        scons defconfig build_foo/bar build_opts/MIPS
-
-
-        guiconfig:
-        Opens the guiconfig editor which will let you view and edit config
-        values, and view help text. guiconfig runs as a graphical application.
-
-        scons guiconfig build_foo/bar
-
-
-        listnewconfig:
-        Lists config options which are new in the Kconfig and which are not
-        currently set in the existing config file.
-
-        scons listnewconfig build_foo/bar
-
-
-        menuconfig:
-        Opens the menuconfig editor which will let you view and edit config
-        values, and view help text. menuconfig runs in text mode.
-
-        scons menuconfig build_foo/bar
-
-
-        oldconfig:
-        Update an existing config by adding settings for new options. This is
-        the same as the olddefconfig tool, except it asks what values you want
-        for the new settings.
-
-        scons oldconfig build_foo/bar
-
-
-        olddefconfig:
-        Update an existing config by adding settings for new options. This is
-        the same as the oldconfig tool, except it uses the default for any new
-        setting.
-
-        scons olddefconfig build_foo/bar
-
-
-        savedefconfig:
-        Save a defconfig file which would give rise to the current config.
-        For instance, you could use menuconfig to set up a config how you want
-        it with the options you cared about, and then use savedefconfig to save
-        a minimal config file. These files would be suitable to use in the
-        defconfig directory. The second argument specifies the filename for
-        the new defconfig file.
-
-        scons savedefconfig build_foo/bar new_def_config
-
-
-        setconfig:
-        Set values in an existing config directory as specified on the command
-        line. For example, to enable gem5's built in systemc kernel:
-
-        scons setconfig build_foo/bar USE_SYSTEMC=y
-""", append=True)
+# helper function: find last occurrence of element in list
+def rfind(l, elt, offs = -1):
+    for i in range(len(l)+offs, 0, -1):
+        if l[i] == elt:
+            return i
+    raise ValueError("element not found")
 
 # Take a list of paths (or SCons Nodes) and return a list with all
 # paths made absolute and ~-expanded.  Paths will be interpreted
 # relative to the launch directory unless a different root is provided
-
-def makePathAbsolute(path, root=GetLaunchDir()):
-    return abspath(os.path.join(root, expanduser(str(path))))
 def makePathListAbsolute(path_list, root=GetLaunchDir()):
-    return [makePathAbsolute(p, root) for p in path_list]
+    return [abspath(os.path.join(root, expanduser(str(p))))
+            for p in path_list]
 
-if BUILD_TARGETS and BUILD_TARGETS[0] in kconfig_actions:
-    # The build targets are really arguments for the kconfig action.
-    kconfig_args = BUILD_TARGETS[:]
-    BUILD_TARGETS[:] = []
+# Each target must have 'build' in the interior of the path; the
+# directory below this will determine the build parameters.  For
+# example, for target 'foo/bar/build/X86/arch/x86/blah.do' we
+# recognize that X86 specifies the configuration because it
+# follow 'build' in the build path.
 
-    kconfig_action = kconfig_args[0]
-    if len(kconfig_args) < 2:
-        error(f'Missing arguments for kconfig action {kconfig_action}')
-    dir_to_configure = makePathAbsolute(kconfig_args[1])
+# The funky assignment to "[:]" is needed to replace the list contents
+# in place rather than reassign the symbol to a new list, which
+# doesn't work (obviously!).
+BUILD_TARGETS[:] = makePathListAbsolute(BUILD_TARGETS)
 
-    kconfig_args = kconfig_args[2:]
+# Generate a list of the unique build roots and configs that the
+# collected targets reference.
+variant_paths = set()
+build_root = None
+for t in BUILD_TARGETS:
+    this_build_root, variant = parse_build_path(t)
 
-    variant_paths = {dir_to_configure}
-else:
-    # Each target must have 'build' in the interior of the path; the
-    # directory below this will determine the build parameters.  For
-    # example, for target 'foo/bar/build/X86/arch/x86/blah.do' we
-    # recognize that X86 specifies the configuration because it
-    # follow 'build' in the build path.
+    # Make sure all targets use the same build root.
+    if not build_root:
+        build_root = this_build_root
+    elif this_build_root != build_root:
+        error("build targets not under same build root\n  %s\n  %s" %
+            (build_root, this_build_root))
 
-    # The funky assignment to "[:]" is needed to replace the list contents
-    # in place rather than reassign the symbol to a new list, which
-    # doesn't work (obviously!).
-    BUILD_TARGETS[:] = makePathListAbsolute(BUILD_TARGETS)
+    # Collect all the variants into a set.
+    variant_paths.add(os.path.join('/', build_root, variant))
 
-    # Generate a list of the unique build directories that the collected
-    # targets reference.
-    variant_paths = set(map(parse_build_path, BUILD_TARGETS))
-    kconfig_action = None
+# Make sure build_root exists (might not if this is the first build there)
+if not isdir(build_root):
+    mkdir(build_root)
+main['BUILDROOT'] = build_root
 
 
 ########################################################################
@@ -536,14 +395,10 @@ for variant_path in variant_paths:
     env = main.Clone()
     env['BUILDDIR'] = variant_path
 
-    gem5_build = os.path.join(variant_path, 'gem5.build')
+    gem5_build = os.path.join(build_root, variant_path, 'gem5.build')
     env['GEM5BUILD'] = gem5_build
     Execute(Mkdir(gem5_build))
 
-    config_file = Dir(gem5_build).File('config')
-    kconfig_file = Dir(gem5_build).File('Kconfig')
-    gem5_kconfig_file = Dir('#src').File('Kconfig')
-
     env.SConsignFile(os.path.join(gem5_build, 'sconsign'))
 
     # Set up default C++ compiler flags
@@ -569,16 +424,6 @@ for variant_path in variant_paths:
         with gem5_scons.Configure(env) as conf:
             conf.CheckLinkFlag('-Wl,--as-needed')
 
-        want_libcxx = GetOption('with_libcxx')
-        if want_libcxx:
-            with gem5_scons.Configure(env) as conf:
-                # Try using libc++ if it supports the <filesystem> library.
-                code = '#include <filesystem>\nint main() { return 0; }'
-                if (not conf.CheckCxxFlag('-stdlib=libc++') or
-                    not conf.CheckLinkFlag('-stdlib=libc++', code=code)
-                ):
-                    error('Requested libc++ but it is not usable')
-
         linker = GetOption('linker')
         if linker:
             with gem5_scons.Configure(env) as conf:
@@ -602,13 +447,7 @@ for variant_path in variant_paths:
                     conf.CheckLinkFlag(
                             '-Wl,--thread-count=%d' % GetOption('num_jobs'))
 
-        with gem5_scons.Configure(env) as conf:
-            ld_optimize_memory_usage = GetOption('limit_ld_memory_usage')
-            if ld_optimize_memory_usage:
-                if conf.CheckLinkFlag('-Wl,--no-keep-memory'):
-                    env.Append(LINKFLAGS=['-Wl,--no-keep-memory'])
-                else:
-                    error("Unable to use --no-keep-memory with the linker")
+
     else:
         error('\n'.join((
               "Don't know what compiler options to use for your compiler.",
@@ -624,8 +463,8 @@ for variant_path in variant_paths:
               "src/SConscript to support that compiler.")))
 
     if env['GCC']:
-        if compareVersions(env['CXXVERSION'], "10") < 0:
-            error('gcc version 10 or newer required.\n'
+        if compareVersions(env['CXXVERSION'], "7") < 0:
+            error('gcc version 7 or newer required.\n'
                   'Installed version:', env['CXXVERSION'])
 
         # Add the appropriate Link-Time Optimization (LTO) flags if
@@ -649,6 +488,17 @@ for variant_path in variant_paths:
             '-fno-builtin-malloc', '-fno-builtin-calloc',
             '-fno-builtin-realloc', '-fno-builtin-free'])
 
+        if compareVersions(env['CXXVERSION'], "9") < 0:
+            # `libstdc++fs`` must be explicitly linked for `std::filesystem``
+            # in GCC version 8. As of GCC version 9, this is not required.
+            #
+            # In GCC 7 the `libstdc++fs`` library explicit linkage is also
+            # required but the `std::filesystem` is under the `experimental`
+            # namespace(`std::experimental::filesystem`).
+            #
+            # Note: gem5 does not support GCC versions < 7.
+            env.Append(LIBS=['stdc++fs'])
+
     elif env['CLANG']:
         if compareVersions(env['CXXVERSION'], "6") < 0:
             error('clang version 6 or newer required.\n'
@@ -666,7 +516,7 @@ for variant_path in variant_paths:
 
         env.Append(TCMALLOC_CCFLAGS=['-fno-builtin'])
 
-        if not want_libcxx and compareVersions(env['CXXVERSION'], "11") < 0:
+        if compareVersions(env['CXXVERSION'], "11") < 0:
             # `libstdc++fs`` must be explicitly linked for `std::filesystem``
             # in clang versions 6 through 10.
             #
@@ -680,7 +530,7 @@ for variant_path in variant_paths:
 
         # On Mac OS X/Darwin we need to also use libc++ (part of XCode) as
         # opposed to libstdc++, as the later is dated.
-        if not want_libcxx and sys.platform == "darwin":
+        if sys.platform == "darwin":
             env.Append(CXXFLAGS=['-stdlib=libc++'])
             env.Append(LIBS=['c++'])
 
@@ -689,37 +539,27 @@ for variant_path in variant_paths:
     if GetOption('with_ubsan'):
         sanitizers.append('undefined')
     if GetOption('with_asan'):
-        if env['GCC']:
-            # Address sanitizer is not supported with GCC. Please see Github
-            # Issue https://github.com/gem5/gem5/issues/916 for more details.
-            warning("Address Sanitizer is not supported with GCC. "
-                    "This option will be ignored.")
-        else:
-            # Available for llvm >= 3.1. A requirement by the build system.
-            sanitizers.append('address')
-            suppressions_file = Dir('util').File('lsan-suppressions')\
-                                .get_abspath()
-            suppressions_opt = 'suppressions=%s' % suppressions_file
-            suppressions_opts = ':'.join([suppressions_opt,
-                                        'print_suppressions=0'])
-            env['ENV']['LSAN_OPTIONS'] = suppressions_opts
-            print()
-            warning('To suppress false positive leaks, set the LSAN_OPTIONS '
-                    'environment variable to "%s" when running gem5' %
-                    suppressions_opts)
-            warning('LSAN_OPTIONS=%s' % suppressions_opts)
-            print()
+        # Available for gcc >= 5 or llvm >= 3.1 both a requirement
+        # by the build system
+        sanitizers.append('address')
+        suppressions_file = Dir('util').File('lsan-suppressions').get_abspath()
+        suppressions_opt = 'suppressions=%s' % suppressions_file
+        suppressions_opts = ':'.join([suppressions_opt,
+                                      'print_suppressions=0'])
+        env['ENV']['LSAN_OPTIONS'] = suppressions_opts
+        print()
+        warning('To suppress false positive leaks, set the LSAN_OPTIONS '
+                'environment variable to "%s" when running gem5' %
+                suppressions_opts)
+        warning('LSAN_OPTIONS=%s' % suppressions_opts)
+        print()
     if sanitizers:
         sanitizers = ','.join(sanitizers)
         if env['GCC'] or env['CLANG']:
-            libsan = (
-                ['-static-libubsan', '-static-libasan']
-                if env['GCC']
-                else ['-static-libsan']
-            )
             env.Append(CCFLAGS=['-fsanitize=%s' % sanitizers,
                                  '-fno-omit-frame-pointer'],
-                       LINKFLAGS=['-fsanitize=%s' % sanitizers] + libsan)
+                        LINKFLAGS=['-fsanitize=%s' % sanitizers,
+                                   '-static-libasan'])
 
             if main["BIN_TARGET_ARCH"] == "x86_64":
                 # Sanitizers can enlarge binary size drammatically, north of
@@ -786,7 +626,7 @@ for variant_path in variant_paths:
                 LINKFLAGS=['-Wl,--no-as-needed', '-lprofiler',
                     '-Wl,--as-needed'])
 
-    env['HAVE_PKG_CONFIG'] = env.Detect('pkg-config') == 'pkg-config'
+    env['HAVE_PKG_CONFIG'] = env.Detect('pkg-config')
 
     with gem5_scons.Configure(env) as conf:
         # On Solaris you need to use libsocket for socket ops
@@ -830,13 +670,59 @@ for variant_path in variant_paths:
         after_sconsopts_callbacks.append(cb)
     Export('AfterSConsopts')
 
-    extras_file = os.path.join(gem5_build, 'extras')
-    extras_var = Variables(extras_file, args=ARGUMENTS)
+    # Sticky variables get saved in the variables file so they persist from
+    # one invocation to the next (unless overridden, in which case the new
+    # value becomes sticky).
+    sticky_vars = Variables(args=ARGUMENTS)
+    Export('sticky_vars')
 
-    extras_var.Add(('EXTRAS', 'Add extra directories to the compilation', ''))
+    # EXTRAS is special since it affects what SConsopts need to be read.
+    sticky_vars.Add(('EXTRAS', 'Add extra directories to the compilation', ''))
+
+    # Set env variables according to the build directory config.
+    sticky_vars.files = []
+    # Variables for $BUILD_ROOT/$VARIANT_DIR are stored in
+    # $BUILD_ROOT/$VARIANT_DIR/gem5.build/variables
+
+    gem5_build_vars = os.path.join(gem5_build, 'variables')
+    build_root_vars = os.path.join(build_root, 'variables', variant_dir)
+    current_vars_files = [gem5_build_vars, build_root_vars]
+    existing_vars_files = list(filter(isfile, current_vars_files))
+    if existing_vars_files:
+        sticky_vars.files.extend(existing_vars_files)
+        if not GetOption('silent'):
+            print('Using saved variables file(s) %s' %
+                    ', '.join(existing_vars_files))
+    else:
+        # Variant specific variables file doesn't exist.
+
+        # Get default build variables from source tree.  Variables are
+        # normally determined by name of $VARIANT_DIR, but can be
+        # overridden by '--default=' arg on command line.
+        default = GetOption('default')
+        opts_dir = Dir('#build_opts').abspath
+        if default:
+            default_vars_files = [
+                    gem5_build_vars,
+                    build_root_vars,
+                    os.path.join(opts_dir, default)
+                ]
+        else:
+            default_vars_files = [os.path.join(opts_dir, variant_dir)]
+        existing_default_files = list(filter(isfile, default_vars_files))
+        if existing_default_files:
+            default_vars_file = existing_default_files[0]
+            sticky_vars.files.append(default_vars_file)
+            print("Variables file(s) %s not found,\n  using defaults in %s" %
+                    (' or '.join(current_vars_files), default_vars_file))
+        else:
+            error("Cannot find variables file(s) %s or default file(s) %s" %
+                    (' or '.join(current_vars_files),
+                     ' or '.join(default_vars_files)))
+            Exit(1)
 
     # Apply current settings for EXTRAS to env.
-    extras_var.Update(env)
+    sticky_vars.Update(env)
 
     # Parse EXTRAS variable to build list of all directories where we're
     # look for sources etc.  This list is exported as extras_dir_list.
@@ -847,17 +733,6 @@ for variant_path in variant_paths:
 
     Export('extras_dir_list')
 
-    # Generate a Kconfig that will source the main gem5 one, and any in any
-    # EXTRAS directories.
-    kconfig_base_py = Dir('#build_tools').File('kconfig_base.py')
-    kconfig_base_cmd_parts = [f'"{kconfig_base_py}" "{kconfig_file.abspath}"',
-            f'"{gem5_kconfig_file.abspath}"']
-    for ed in extras_dir_list:
-        kconfig_base_cmd_parts.append(f'"{ed}"')
-    kconfig_base_cmd = ' '.join(kconfig_base_cmd_parts)
-    if env.Execute(kconfig_base_cmd) != 0:
-        error("Failed to build base Kconfig file")
-
     # Variables which were determined with Configure.
     env['CONF'] = {}
 
@@ -885,48 +760,24 @@ for variant_path in variant_paths:
     for cb in after_sconsopts_callbacks:
         cb()
 
-    # Handle any requested kconfig action, then exit.
-    if kconfig_action:
-        if kconfig_action == 'defconfig':
-            if len(kconfig_args) != 1:
-                error('Usage: scons defconfig <build dir> <defconfig file>')
-            defconfig_path = makePathAbsolute(kconfig_args[0])
-            kconfig.defconfig(env, kconfig_file.abspath,
-                    defconfig_path, config_file.abspath)
-        elif kconfig_action == 'guiconfig':
-            kconfig.guiconfig(env, kconfig_file.abspath, config_file.abspath,
-                    variant_path)
-        elif kconfig_action == 'listnewconfig':
-            kconfig.listnewconfig(env, kconfig_file.abspath,
-                    config_file.abspath)
-        elif kconfig_action == 'menuconfig':
-            kconfig.menuconfig(env, kconfig_file.abspath, config_file.abspath,
-                    variant_path)
-        elif kconfig_action == 'oldconfig':
-            kconfig.oldconfig(env, kconfig_file.abspath, config_file.abspath)
-        elif kconfig_action == 'olddefconfig':
-            kconfig.olddefconfig(env, kconfig_file.abspath,
-                    config_file.abspath)
-        elif kconfig_action == 'savedefconfig':
-            if len(kconfig_args) != 1:
-                error('Usage: scons defconfig <build dir> <defconfig file>')
-            defconfig_path = makePathAbsolute(kconfig_args[0])
-            kconfig.savedefconfig(env, kconfig_file.abspath,
-                    config_file.abspath, defconfig_path)
-        elif kconfig_action == 'setconfig':
-            kconfig.setconfig(env, kconfig_file.abspath, config_file.abspath,
-                    ARGUMENTS)
-        Exit(0)
+    # Update env for new variables added by the SConsopts.
+    sticky_vars.Update(env)
 
-    # If no config exists yet, see if we know how to make one?
-    if not isfile(config_file.abspath):
-        buildopts_file = Dir('#build_opts').File(variant_dir)
-        if not isfile(buildopts_file.abspath):
-            error('No config found, and no implicit config recognized')
-        kconfig.defconfig(env, kconfig_file.abspath, buildopts_file.abspath,
-                config_file.abspath)
+    Help('''
+Build variables for {dir}:
+{help}
+'''.format(dir=variant_dir, help=sticky_vars.GenerateHelpText(env)),
+         append=True)
 
-    kconfig.update_env(env, kconfig_file.abspath, config_file.abspath)
+    # If the old vars file exists, delete it to avoid confusion/stale values.
+    if isfile(build_root_vars):
+        warning(f'Deleting old variant variables file "{build_root_vars}"')
+        remove(build_root_vars)
+    # Save sticky variables back to the gem5.build variant variables file.
+    sticky_vars.Save(gem5_build_vars, env)
+
+    # Pull all the sticky variables into the CONF dict.
+    env['CONF'].update({key: env[key] for key in sticky_vars.keys()})
 
     # Do this after we save setting back, or else we'll tack on an
     # extra 'qdo' every time we run scons.

build_opts/ALL

@@ -1,22 +1,7 @@
-RUBY=y
-USE_MULTIPLE_PROTOCOLS=y
-PROTOCOL="MULTIPLE"
-RUBY_PROTOCOL_MOESI_AMD_Base=y
-RUBY_PROTOCOL_MESI_Two_Level=y
-RUBY_PROTOCOL_MESI_Three_Level=y
-RUBY_PROTOCOL_MESI_Three_Level_HTM=y
-RUBY_PROTOCOL_MI_example=y
-RUBY_PROTOCOL_MOESI_CMP_directory=y
-RUBY_PROTOCOL_MOESI_CMP_token=y
-RUBY_PROTOCOL_MOESI_hammer=y
-RUBY_PROTOCOL_Garnet_standalone=y
-RUBY_PROTOCOL_CHI=y
-RUBY_PROTOCOL_MSI=y
-BUILD_ISA=y
-USE_ARM_ISA=y
-USE_MIPS_ISA=y
-USE_POWER_ISA=y
-USE_RISCV_ISA=y
-USE_SPARC_ISA=y
-USE_X86_ISA=y
-USE_TEST_OBJECTS=y
+USE_ARM_ISA = True
+USE_MIPS_ISA = True
+USE_POWER_ISA = True
+USE_RISCV_ISA = True
+USE_SPARC_ISA = True
+USE_X86_ISA = True
+PROTOCOL = 'MESI_Two_Level'

build_opts/ARM

@@ -1,5 +1,2 @@
-BUILD_ISA=y
-USE_ARM_ISA=y
-RUBY=y
-PROTOCOL="CHI"
-RUBY_PROTOCOL_CHI=y
+USE_ARM_ISA = True
+PROTOCOL = 'CHI'

build_opts/ARM_MESI_Three_Level

@@ -1,5 +1,5 @@
-BUILD_ISA=y
-USE_ARM_ISA=y
-RUBY=y
-PROTOCOL="MESI_Three_Level"
-RUBY_PROTOCOL_MESI_Three_Level=y
+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+
+USE_ARM_ISA = True
+PROTOCOL = 'MESI_Three_Level'

build_opts/ARM_MESI_Three_Level_HTM

@@ -1,5 +1,5 @@
-BUILD_ISA=y
-USE_ARM_ISA=y
-RUBY=y
-PROTOCOL="MESI_Three_Level_HTM"
-RUBY_PROTOCOL_MESI_Three_Level_HTM=y
+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+
+USE_ARM_ISA = True
+PROTOCOL = 'MESI_Three_Level_HTM'

build_opts/ARM_MOESI_hammer

@@ -1,5 +1,5 @@
-BUILD_ISA=y
-USE_ARM_ISA=y
-RUBY=y
-PROTOCOL="MOESI_hammer"
-RUBY_PROTOCOL_MOESI_hammer=y
+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+
+USE_ARM_ISA = True
+PROTOCOL = 'MOESI_hammer'

build_opts/ARM_X86

@@ -1,6 +0,0 @@
-BUILD_ISA=y
-USE_ARM_ISA=y
-USE_X86_ISA=y
-RUBY=y
-PROTOCOL="MESI_Two_Level"
-RUBY_PROTOCOL_MESI_Two_Level=y

build_opts/GCN3_X86

@@ -0,0 +1,4 @@
+PROTOCOL = 'GPU_VIPER'
+USE_X86_ISA = True
+TARGET_GPU_ISA = 'gcn3'
+BUILD_GPU = True

build_opts/Garnet_standalone

@@ -1,3 +1,2 @@
-RUBY=y
-PROTOCOL="Garnet_standalone"
-RUBY_PROTOCOL_Garnet_standalone=y
+USE_NULL_ISA = True
+PROTOCOL = 'Garnet_standalone'

build_opts/MIPS

@@ -1,5 +1,2 @@
-RUBY=y
-PROTOCOL="MI_example"
-RUBY_PROTOCOL_MI_example=y
-BUILD_ISA=y
-USE_MIPS_ISA=y
+USE_MIPS_ISA = True
+PROTOCOL = 'MI_example'

build_opts/NULL

@@ -1,3 +1,2 @@
-RUBY=y
-PROTOCOL="MI_example"
-RUBY_PROTOCOL_MI_example=y
+USE_NULL_ISA = True
+PROTOCOL='MI_example'

build_opts/NULL_ALL_RUBY

@@ -1,14 +0,0 @@
-RUBY=y
-USE_MULTIPLE_PROTOCOLS=y
-PROTOCOL="MULTIPLE"
-RUBY_PROTOCOL_MOESI_AMD_Base=y
-RUBY_PROTOCOL_MESI_Two_Level=y
-RUBY_PROTOCOL_MESI_Three_Level=y
-RUBY_PROTOCOL_MESI_Three_Level_HTM=y
-RUBY_PROTOCOL_MI_example=y
-RUBY_PROTOCOL_MOESI_CMP_directory=y
-RUBY_PROTOCOL_MOESI_CMP_token=y
-RUBY_PROTOCOL_MOESI_hammer=y
-RUBY_PROTOCOL_Garnet_standalone=y
-RUBY_PROTOCOL_CHI=y
-RUBY_PROTOCOL_MSI=y

build_opts/NULL_MESI_Two_Level

@@ -1,3 +1,2 @@
-RUBY=y
-PROTOCOL="MESI_Two_Level"
-RUBY_PROTOCOL_MESI_Two_Level=y
+USE_NULL_ISA = True
+PROTOCOL = 'MESI_Two_Level'

build_opts/NULL_MOESI_CMP_directory

@@ -1,3 +1,2 @@
-RUBY=y
-PROTOCOL="MOESI_CMP_directory"
-RUBY_PROTOCOL_MOESI_CMP_directory=y
+USE_NULL_ISA = True
+PROTOCOL='MOESI_CMP_directory'

build_opts/NULL_MOESI_CMP_token

@@ -1,3 +1,2 @@
-RUBY=y
-PROTOCOL="MOESI_CMP_token"
-RUBY_PROTOCOL_MOESI_CMP_token=y
+USE_NULL_ISA = True
+PROTOCOL='MOESI_CMP_token'

build_opts/NULL_MOESI_hammer

@@ -1,3 +1,2 @@
-RUBY=y
-PROTOCOL="MOESI_hammer"
-RUBY_PROTOCOL_MOESI_hammer=y
+USE_NULL_ISA = True
+PROTOCOL='MOESI_hammer'

build_opts/POWER

@@ -1,5 +1,2 @@
-RUBY=y
-PROTOCOL="MI_example"
-RUBY_PROTOCOL_MI_example=y
-BUILD_ISA=y
-USE_POWER_ISA=y
+USE_POWER_ISA = True
+PROTOCOL = 'MI_example'

build_opts/RISCV

@@ -1,5 +1,2 @@
-RUBY=y
-PROTOCOL="MI_example"
-RUBY_PROTOCOL_MI_example=y
-BUILD_ISA=y
-USE_RISCV_ISA=y
+USE_RISCV_ISA = True
+PROTOCOL = 'MI_example'

build_opts/SPARC

@@ -1,5 +1,2 @@
-RUBY=y
-PROTOCOL="MI_example"
-RUBY_PROTOCOL_MI_example=y
-BUILD_ISA=y
-USE_SPARC_ISA=y
+USE_SPARC_ISA = True
+PROTOCOL = 'MI_example'

build_opts/VEGA_X86

@@ -1,8 +1,4 @@
-RUBY=y
-NUMBER_BITS_PER_SET=128
-PROTOCOL="GPU_VIPER"
-RUBY_PROTOCOL_GPU_VIPER=y
-BUILD_ISA=y
-USE_X86_ISA=y
-VEGA_GPU_ISA=y
-BUILD_GPU=y
+PROTOCOL = 'GPU_VIPER'
+USE_X86_ISA = True
+TARGET_GPU_ISA = 'vega'
+BUILD_GPU = True

build_opts/X86

@@ -1,6 +1,3 @@
-RUBY=y
-NUMBER_BITS_PER_SET=128
-PROTOCOL="MESI_Two_Level"
-RUBY_PROTOCOL_MESI_Two_Level=y
-BUILD_ISA=y
-USE_X86_ISA=y
+USE_X86_ISA = True
+PROTOCOL = 'MESI_Two_Level'
+NUMBER_BITS_PER_SET = '128'

build_opts/X86_MESI_Two_Level

@@ -1,6 +1,3 @@
-RUBY=y
-NUMBER_BITS_PER_SET=128
-PROTOCOL="MESI_Two_Level"
-RUBY_PROTOCOL_MESI_Two_Level=y
-BUILD_ISA=y
-USE_X86_ISA=y
+USE_X86_ISA = True
+PROTOCOL = 'MESI_Two_Level'
+NUMBER_BITS_PER_SET = '128'

build_opts/X86_MI_example

@@ -1,5 +1,2 @@
-RUBY=y
-PROTOCOL="MI_example"
-RUBY_PROTOCOL_MI_example=y
-BUILD_ISA=y
-USE_X86_ISA=y
+USE_X86_ISA = True
+PROTOCOL = 'MI_example'

build_opts/X86_MOESI_AMD_Base

@@ -1,5 +1,2 @@
-RUBY=y
-PROTOCOL="MOESI_AMD_Base"
-RUBY_PROTOCOL_MOESI_AMD_Base=y
-BUILD_ISA=y
-USE_X86_ISA=y
+PROTOCOL = 'MOESI_AMD_Base'
+USE_X86_ISA = True

build_tools/code_formatter.py

@@ -46,7 +46,7 @@ import os
 import re
 
 
-class lookup:
+class lookup(object):
     def __init__(self, formatter, frame, *args, **kwargs):
         self.frame = frame
         self.formatter = formatter
@@ -106,7 +106,7 @@ class code_formatter_meta(type):
     """
 
     def __init__(cls, name, bases, dct):
-        super().__init__(name, bases, dct)
+        super(code_formatter_meta, cls).__init__(name, bases, dct)
         if "pattern" in dct:
             pat = cls.pattern
         else:
@@ -125,7 +125,7 @@ class code_formatter_meta(type):
         cls.pattern = re.compile(pat, re.VERBOSE | re.DOTALL | re.MULTILINE)
 
 
-class code_formatter(metaclass=code_formatter_meta):
+class code_formatter(object, metaclass=code_formatter_meta):
     delim = r"$"
     ident = r"[_A-z]\w*"
     pos = r"[0-9]+"
@@ -272,7 +272,7 @@ class code_formatter(metaclass=code_formatter_meta):
             # check for a lone identifier
             if ident:
                 indent = match.group("indent")  # must be spaces
-                lone = f"{l[ident]}"
+                lone = "%s" % (l[ident],)
 
                 def indent_lines(gen):
                     for line in gen:
@@ -284,7 +284,7 @@ class code_formatter(metaclass=code_formatter_meta):
             # check for an identifier, braced or not
             ident = match.group("ident") or match.group("b_ident")
             if ident is not None:
-                return f"{l[ident]}"
+                return "%s" % (l[ident],)
 
             # check for a positional parameter, braced or not
             pos = match.group("pos") or match.group("b_pos")
@@ -295,13 +295,13 @@ class code_formatter(metaclass=code_formatter_meta):
                         "Positional parameter #%d not found in pattern" % pos,
                         code_formatter.pattern,
                     )
-                return f"{args[int(pos)]}"
+                return "%s" % (args[int(pos)],)
 
             # check for a double braced expression
             eval_expr = match.group("eval")
             if eval_expr is not None:
                 result = eval(eval_expr, {}, l)
-                return f"{result}"
+                return "%s" % (result,)
 
             # check for an escaped delimiter
             if match.group("escaped") is not None:

build_tools/cxx_config_cc.py

@@ -3,7 +3,6 @@
 # Copyright 2013 Mark D. Hill and David A. Wood
 # Copyright 2017-2020 ARM Limited
 # Copyright 2021 Google, Inc.
-# Copyright 2023 COSEDA Technologies GmbH
 #
 # The license below extends only to copyright in the software and shall
 # not be construed as granting a license to any other intellectual
@@ -43,6 +42,7 @@ import os.path
 import sys
 
 import importer
+
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
@@ -58,8 +58,8 @@ importer.install()
 module = importlib.import_module(args.modpath)
 sim_object = getattr(module, sim_object_name)
 
-import m5.params
 from m5.params import isSimObjectClass
+import m5.params
 
 code = code_formatter()
 
@@ -104,7 +104,7 @@ for param in sim_object._params.values():
 
 for port in sim_object._ports.values():
     is_vector = isinstance(port, m5.params.VectorPort)
-    is_requestor = port.is_source
+    is_requestor = port.role == "GEM5 REQUESTOR"
 
     code(
         'ports["%s"] = new PortDesc("%s", %s, %s);'

build_tools/cxx_config_hh.py

@@ -42,6 +42,7 @@ import os.path
 import sys
 
 import importer
+
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()

build_tools/debugflaghh.py

@@ -100,16 +100,13 @@ if components:
 inline union ${{args.name}}
 {
     ~${{args.name}}() {}
-
-    CompoundFlag flag${{args.name}};
-
-    ${{args.name}}() : flag${{args.name}}("${{args.name}}", "${{args.desc}}",
-        {
+    CompoundFlag ${{args.name}} = {
+        "${{args.name}}", "${{args.desc}}", {
             ${{",\\n            ".join(
                 f"(Flag *)&::gem5::debug::{flag}" for flag in components)}}
-        }) {}
-
-} instance${{args.name}};
+        }
+    };
+} ${{args.name}};
 """
     )
 else:
@@ -118,11 +115,10 @@ else:
 inline union ${{args.name}}
 {
     ~${{args.name}}() {}
-    SimpleFlag flag${{args.name}};
-
-    ${{args.name}}() : flag${{args.name}}("${{args.name}}", "${{args.desc}}", ${{"true" if fmt else "false"}}) {}
-
-} instance${{args.name}};
+    SimpleFlag ${{args.name}} = {
+        "${{args.name}}", "${{args.desc}}", ${{"true" if fmt else "false"}}
+    };
+} ${{args.name}};
 """
     )
 
@@ -131,7 +127,7 @@ code(
 } // namespace unions
 
 inline constexpr const auto& ${{args.name}} =
-    ::gem5::debug::unions::instance${{args.name}}.flag${{args.name}};
+    ::gem5::debug::unions::${{args.name}}.${{args.name}};
 
 } // namespace debug
 } // namespace gem5

build_tools/enum_cc.py

@@ -42,6 +42,7 @@ import os.path
 import sys
 
 import importer
+
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
@@ -117,6 +118,7 @@ code("} // namespace gem5")
 
 
 if use_python:
+
     name = enum.__name__
     enum_name = enum.__name__ if enum.enum_name is None else enum.enum_name
     wrapper_name = enum_name if enum.is_class else enum.wrapper_name

build_tools/enum_hh.py

@@ -42,6 +42,7 @@ import os.path
 import sys
 
 import importer
+
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
@@ -65,7 +66,7 @@ code = code_formatter()
 wrapper_name = enum.wrapper_name
 wrapper = "struct" if enum.wrapper_is_struct else "namespace"
 name = enum.__name__ if enum.enum_name is None else enum.enum_name
-idem_macro = f"__ENUM__{wrapper_name}__{name}__"
+idem_macro = "__ENUM__%s__%s__" % (wrapper_name, name)
 
 code(
     """\

build_tools/grammar.py

@@ -36,7 +36,7 @@ class ParseError(Exception):
         self.token = token
 
 
-class Grammar:
+class Grammar(object):
     def setupLexerFactory(self, **kwargs):
         if "module" in kwargs:
             raise AttributeError("module is an illegal attribute")
@@ -92,7 +92,7 @@ class Grammar:
             return self.current_lexer.lineno
 
         raise AttributeError(
-            f"'{type(self)}' object has no attribute '{attr}'"
+            "'%s' object has no attribute '%s'" % (type(self), attr)
         )
 
     def parse_string(self, data, source="<string>", debug=None, tracking=0):
@@ -118,7 +118,7 @@ class Grammar:
     def parse_file(self, f, **kwargs):
         if isinstance(f, str):
             source = f
-            f = open(f)
+            f = open(f, "r")
         elif isinstance(f, file):
             source = f.name
         else:
@@ -137,7 +137,7 @@ class Grammar:
                 t.value,
             )
         else:
-            msg = f"Syntax error at end of {self.current_source}"
+            msg = "Syntax error at end of %s" % (self.current_source,)
         raise ParseError(msg, t)
 
     def t_error(self, t):

build_tools/infopy.py

@@ -56,7 +56,7 @@ for source in args.files:
     # `README.md = "..."` which is not valid as `md` is not a property of
     # `README`.
     src = os.path.basename(source).replace(".", "_")
-    with open(source) as f:
+    with open(source, "r") as f:
         data = "".join(f)
     code("${src} = ${{repr(data)}}")
 

build_tools/marshal.py

@@ -74,7 +74,7 @@ if "LC_CTYPE" in os.environ:
 
 _, cpp, python, modpath, abspath = sys.argv
 
-with open(python) as f:
+with open(python, "r") as f:
     src = f.read()
 
 compiled = compile(src, python, "exec")

build_tools/sim_object_param_struct_cc.py

@@ -42,6 +42,7 @@ import os.path
 import sys
 
 import importer
+
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
@@ -87,6 +88,7 @@ ports = sim_object._ports.local
 
 # only include pybind if python is enabled in the build
 if use_python:
+
     code(
         """#include "pybind11/pybind11.h"
 #include "pybind11/stl.h"

build_tools/sim_object_param_struct_hh.py

@@ -42,6 +42,7 @@ import os.path
 import sys
 
 import importer
+
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
@@ -80,7 +81,7 @@ except:
 warned_about_nested_templates = False
 
 
-class CxxClass:
+class CxxClass(object):
     def __init__(self, sig, template_params=[]):
         # Split the signature into its constituent parts. This could
         # potentially be done with regular expressions, but
@@ -211,7 +212,8 @@ code.indent()
 if sim_object == SimObject:
     code(
         """
-virtual ~SimObjectParams() = default;
+SimObjectParams() {}
+virtual ~SimObjectParams() {}
 
 std::string name;
     """

configs/common/Benchmarks.py

@@ -24,14 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from common.SysPaths import script, disk, binary
 from os import environ as env
-
-from common.SysPaths import (
-    binary,
-    disk,
-    script,
-)
-
 from m5.defines import buildEnv
 
 
@@ -55,7 +49,7 @@ class SysConfig:
         if self.memsize:
             return self.memsize
         else:
-            return "128MiB"
+            return "128MB"
 
     def disks(self):
         if self.disknames:
@@ -77,8 +71,8 @@ class SysConfig:
 # The first defined machine is the test system, the others are driving systems
 
 Benchmarks = {
-    "PovrayBench": [SysConfig("povray-bench.rcS", "512MiB", ["povray.img"])],
-    "PovrayAutumn": [SysConfig("povray-autumn.rcS", "512MiB", ["povray.img"])],
+    "PovrayBench": [SysConfig("povray-bench.rcS", "512MB", ["povray.img"])],
+    "PovrayAutumn": [SysConfig("povray-autumn.rcS", "512MB", ["povray.img"])],
     "NetperfStream": [
         SysConfig("netperf-stream-client.rcS"),
         SysConfig("netperf-server.rcS"),
@@ -97,55 +91,55 @@ Benchmarks = {
         SysConfig("netperf-server.rcS"),
     ],
     "SurgeStandard": [
-        SysConfig("surge-server.rcS", "512MiB"),
-        SysConfig("surge-client.rcS", "256MiB"),
+        SysConfig("surge-server.rcS", "512MB"),
+        SysConfig("surge-client.rcS", "256MB"),
     ],
     "SurgeSpecweb": [
-        SysConfig("spec-surge-server.rcS", "512MiB"),
-        SysConfig("spec-surge-client.rcS", "256MiB"),
+        SysConfig("spec-surge-server.rcS", "512MB"),
+        SysConfig("spec-surge-client.rcS", "256MB"),
     ],
     "Nhfsstone": [
-        SysConfig("nfs-server-nhfsstone.rcS", "512MiB"),
+        SysConfig("nfs-server-nhfsstone.rcS", "512MB"),
         SysConfig("nfs-client-nhfsstone.rcS"),
     ],
     "Nfs": [
-        SysConfig("nfs-server.rcS", "900MiB"),
+        SysConfig("nfs-server.rcS", "900MB"),
         SysConfig("nfs-client-dbench.rcS"),
     ],
     "NfsTcp": [
-        SysConfig("nfs-server.rcS", "900MiB"),
+        SysConfig("nfs-server.rcS", "900MB"),
         SysConfig("nfs-client-tcp.rcS"),
     ],
     "IScsiInitiator": [
-        SysConfig("iscsi-client.rcS", "512MiB"),
-        SysConfig("iscsi-server.rcS", "512MiB"),
+        SysConfig("iscsi-client.rcS", "512MB"),
+        SysConfig("iscsi-server.rcS", "512MB"),
     ],
     "IScsiTarget": [
-        SysConfig("iscsi-server.rcS", "512MiB"),
-        SysConfig("iscsi-client.rcS", "512MiB"),
+        SysConfig("iscsi-server.rcS", "512MB"),
+        SysConfig("iscsi-client.rcS", "512MB"),
     ],
     "Validation": [
-        SysConfig("iscsi-server.rcS", "512MiB"),
-        SysConfig("iscsi-client.rcS", "512MiB"),
+        SysConfig("iscsi-server.rcS", "512MB"),
+        SysConfig("iscsi-client.rcS", "512MB"),
     ],
     "Ping": [SysConfig("ping-server.rcS"), SysConfig("ping-client.rcS")],
-    "ValAccDelay": [SysConfig("devtime.rcS", "512MiB")],
-    "ValAccDelay2": [SysConfig("devtimewmr.rcS", "512MiB")],
-    "ValMemLat": [SysConfig("micro_memlat.rcS", "512MiB")],
-    "ValMemLat2MB": [SysConfig("micro_memlat2mb.rcS", "512MiB")],
-    "ValMemLat8MB": [SysConfig("micro_memlat8mb.rcS", "512MiB")],
-    "ValMemLat": [SysConfig("micro_memlat8.rcS", "512MiB")],
-    "ValTlbLat": [SysConfig("micro_tlblat.rcS", "512MiB")],
-    "ValSysLat": [SysConfig("micro_syscall.rcS", "512MiB")],
-    "ValCtxLat": [SysConfig("micro_ctx.rcS", "512MiB")],
-    "ValStream": [SysConfig("micro_stream.rcS", "512MiB")],
-    "ValStreamScale": [SysConfig("micro_streamscale.rcS", "512MiB")],
-    "ValStreamCopy": [SysConfig("micro_streamcopy.rcS", "512MiB")],
-    "MutexTest": [SysConfig("mutex-test.rcS", "128MiB")],
+    "ValAccDelay": [SysConfig("devtime.rcS", "512MB")],
+    "ValAccDelay2": [SysConfig("devtimewmr.rcS", "512MB")],
+    "ValMemLat": [SysConfig("micro_memlat.rcS", "512MB")],
+    "ValMemLat2MB": [SysConfig("micro_memlat2mb.rcS", "512MB")],
+    "ValMemLat8MB": [SysConfig("micro_memlat8mb.rcS", "512MB")],
+    "ValMemLat": [SysConfig("micro_memlat8.rcS", "512MB")],
+    "ValTlbLat": [SysConfig("micro_tlblat.rcS", "512MB")],
+    "ValSysLat": [SysConfig("micro_syscall.rcS", "512MB")],
+    "ValCtxLat": [SysConfig("micro_ctx.rcS", "512MB")],
+    "ValStream": [SysConfig("micro_stream.rcS", "512MB")],
+    "ValStreamScale": [SysConfig("micro_streamscale.rcS", "512MB")],
+    "ValStreamCopy": [SysConfig("micro_streamcopy.rcS", "512MB")],
+    "MutexTest": [SysConfig("mutex-test.rcS", "128MB")],
     "ArmAndroid-GB": [
         SysConfig(
             "null.rcS",
-            "256MiB",
+            "256MB",
             ["ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img"],
             None,
             "android-gingerbread",
@@ -154,7 +148,7 @@ Benchmarks = {
     "bbench-gb": [
         SysConfig(
             "bbench-gb.rcS",
-            "256MiB",
+            "256MB",
             ["ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img"],
             None,
             "android-gingerbread",
@@ -163,7 +157,7 @@ Benchmarks = {
     "ArmAndroid-ICS": [
         SysConfig(
             "null.rcS",
-            "256MiB",
+            "256MB",
             ["ARMv7a-ICS-Android.SMP.nolock.clean.img"],
             None,
             "android-ics",
@@ -172,7 +166,7 @@ Benchmarks = {
     "bbench-ics": [
         SysConfig(
             "bbench-ics.rcS",
-            "256MiB",
+            "256MB",
             ["ARMv7a-ICS-Android.SMP.nolock.img"],
             None,
             "android-ics",

configs/common/CacheConfig.py

@@ -40,13 +40,13 @@
 # Configure the M5 cache hierarchy config in one place
 #
 
-from common import ObjectList
-from common.Caches import *
-
 import m5
 from m5.objects import *
-
 from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
+
+from common.Caches import *
+from common import ObjectList
 
 
 def _get_hwp(hwp_option):
@@ -117,6 +117,9 @@ def config_cache(options, system):
             None,
         )
 
+        if get_runtime_isa() in [ISA.X86, ISA.RISCV]:
+            walk_cache_class = PageTableWalkerCache
+
     # Set the cache line size of the system
     system.cache_line_size = options.cacheline_size
 
@@ -147,13 +150,11 @@ def config_cache(options, system):
             icache = icache_class(**_get_cache_opts("l1i", options))
             dcache = dcache_class(**_get_cache_opts("l1d", options))
 
-            # If we are using ISA.X86 or ISA.RISCV, we set walker caches.
-            if ObjectList.cpu_list.get_isa(options.cpu_type) in [
-                ISA.RISCV,
-                ISA.X86,
-            ]:
-                iwalkcache = PageTableWalkerCache()
-                dwalkcache = PageTableWalkerCache()
+            # If we have a walker cache specified, instantiate two
+            # instances here
+            if walk_cache_class:
+                iwalkcache = walk_cache_class()
+                dwalkcache = walk_cache_class()
             else:
                 iwalkcache = None
                 dwalkcache = None
@@ -191,11 +192,7 @@ def config_cache(options, system):
             # on these names.  For simplicity, we would advise configuring
             # it to use this naming scheme; if this isn't possible, change
             # the names below.
-            if ObjectList.cpu_list.get_isa(options.cpu_type) in [
-                ISA.X86,
-                ISA.ARM,
-                ISA.RISCV,
-            ]:
+            if get_runtime_isa() in [ISA.X86, ISA.ARM, ISA.RISCV]:
                 system.cpu[i].addPrivateSplitL1Caches(
                     ExternalCache("cpu%d.icache" % i),
                     ExternalCache("cpu%d.dcache" % i),

configs/common/Caches.py

@@ -39,8 +39,8 @@
 
 from m5.defines import buildEnv
 from m5.objects import *
-
 from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 # Base implementations of L1, L2, IO and TLB-walker caches. There are
 # used in the regressions and also as base components in the
@@ -84,7 +84,7 @@ class IOCache(Cache):
     data_latency = 50
     response_latency = 50
     mshrs = 20
-    size = "1KiB"
+    size = "1kB"
     tgts_per_mshr = 12
 
 
@@ -94,6 +94,13 @@ class PageTableWalkerCache(Cache):
     data_latency = 2
     response_latency = 2
     mshrs = 10
-    size = "1KiB"
+    size = "1kB"
     tgts_per_mshr = 12
-    is_read_only = False
+
+    # the x86 table walker actually writes to the table-walker cache
+    if get_runtime_isa() in [ISA.X86, ISA.RISCV]:
+        is_read_only = False
+    else:
+        is_read_only = True
+        # Writeback clean lines as well
+        writeback_clean = True

configs/common/CpuConfig.py

@@ -33,19 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import m5.objects
 from m5 import fatal
-
-from gem5.isas import ISA
-
-isa_string_map = {
-    ISA.X86: "X86",
-    ISA.ARM: "Arm",
-    ISA.RISCV: "Riscv",
-    ISA.SPARC: "Sparc",
-    ISA.POWER: "Power",
-    ISA.MIPS: "Mips",
-}
+import m5.objects
 
 
 def config_etrace(cpu_cls, cpu_list, options):

configs/common/FSConfig.py

@@ -38,13 +38,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from common import ObjectList
-from common.Benchmarks import *
-
 import m5
 import m5.defines
 from m5.objects import *
 from m5.util import *
+from common.Benchmarks import *
+from common import ObjectList
 
 # Populate to reflect supported os types per target ISA
 os_types = set()
@@ -137,8 +136,8 @@ def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
     self.t1000.attachOnChipIO(self.membus)
     self.t1000.attachIO(self.iobus)
     self.mem_ranges = [
-        AddrRange(Addr("1MiB"), size="64MiB"),
-        AddrRange(Addr("2GiB"), size="256MiB"),
+        AddrRange(Addr("1MB"), size="64MB"),
+        AddrRange(Addr("2GB"), size="256MB"),
     ]
     self.bridge.mem_side_port = self.iobus.cpu_side_ports
     self.bridge.cpu_side_port = self.membus.mem_side_ports
@@ -174,21 +173,21 @@ def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
     # ROM for OBP/Reset/Hypervisor
     self.rom = SimpleMemory(
         image_file=binary("t1000_rom.bin"),
-        range=AddrRange(0xFFF0000000, size="8MiB"),
+        range=AddrRange(0xFFF0000000, size="8MB"),
     )
     # nvram
     self.nvram = SimpleMemory(
-        image_file=binary("nvram1"), range=AddrRange(0x1F11000000, size="8KiB")
+        image_file=binary("nvram1"), range=AddrRange(0x1F11000000, size="8kB")
     )
     # hypervisor description
     self.hypervisor_desc = SimpleMemory(
         image_file=binary("1up-hv.bin"),
-        range=AddrRange(0x1F12080000, size="8KiB"),
+        range=AddrRange(0x1F12080000, size="8kB"),
     )
     # partition description
     self.partition_desc = SimpleMemory(
         image_file=binary("1up-md.bin"),
-        range=AddrRange(0x1F12000000, size="8KiB"),
+        range=AddrRange(0x1F12000000, size="8kB"),
     )
 
     self.rom.port = self.membus.mem_side_ports
@@ -423,7 +422,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
     self.iobus = IOXBar()
     self.membus = MemBus()
     self.bridge = Bridge(delay="50ns")
-    self.mem_ranges = [AddrRange("1GiB")]
+    self.mem_ranges = [AddrRange("1GB")]
     self.bridge.mem_side_port = self.iobus.cpu_side_ports
     self.bridge.cpu_side_port = self.membus.mem_side_ports
     self.disks = makeCowDisks(mdesc.disks())
@@ -469,7 +468,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
     x86_sys.bridge.cpu_side_port = x86_sys.membus.mem_side_ports
     # Allow the bridge to pass through:
     #  1) kernel configured PCI device memory map address: address range
-    #     [0xC0000000, 0xFFFF0000). (The upper 64KiB are reserved for m5ops.)
+    #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
     #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
     #  3) everything in the IO address range up to the local APIC, and
     #  4) then the entire PCI address space and beyond.
@@ -526,22 +525,22 @@ def makeX86System(mem_mode, numCPUs=1, mdesc=None, workload=None, Ruby=False):
     # Physical memory
     # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
     # for various devices.  Hence, if the physical memory size is greater than
-    # 3GiB, we need to split it into two parts.
+    # 3GB, we need to split it into two parts.
     excess_mem_size = convert.toMemorySize(mdesc.mem()) - convert.toMemorySize(
-        "3GiB"
+        "3GB"
     )
     if excess_mem_size <= 0:
         self.mem_ranges = [AddrRange(mdesc.mem())]
     else:
         warn(
             "Physical memory size specified is %s which is greater than "
-            "3GiB.  Twice the number of memory controllers would be "
+            "3GB.  Twice the number of memory controllers would be "
             "created." % (mdesc.mem())
         )
 
         self.mem_ranges = [
-            AddrRange("3GiB"),
-            AddrRange(Addr("4GiB"), size=excess_mem_size),
+            AddrRange("3GB"),
+            AddrRange(Addr("4GB"), size=excess_mem_size),
         ]
 
     # Platform
@@ -663,16 +662,16 @@ def makeLinuxX86System(
     # Build up the x86 system and then specialize it for Linux
     self = makeX86System(mem_mode, numCPUs, mdesc, X86FsLinux(), Ruby)
 
-    # We assume below that there's at least 1MiB of memory. We'll require 2
+    # We assume below that there's at least 1MB of memory. We'll require 2
     # just to avoid corner cases.
     phys_mem_size = sum([r.size() for r in self.mem_ranges])
     assert phys_mem_size >= 0x200000
     assert len(self.mem_ranges) <= 2
 
     entries = [
-        # Mark the first mibibyte of memory as reserved
-        X86E820Entry(addr=0, size="639KiB", range_type=1),
-        X86E820Entry(addr=0x9FC00, size="385KiB", range_type=2),
+        # Mark the first megabyte of memory as reserved
+        X86E820Entry(addr=0, size="639kB", range_type=1),
+        X86E820Entry(addr=0x9FC00, size="385kB", range_type=2),
         # Mark the rest of physical memory as available
         X86E820Entry(
             addr=0x100000,
@@ -681,7 +680,7 @@ def makeLinuxX86System(
         ),
     ]
 
-    # Mark [mem_size, 3iB) as reserved if memory less than 3GiB, which force
+    # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
     # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
     # specific range can pass though bridge to iobus.
     if len(self.mem_ranges) == 1:
@@ -693,10 +692,10 @@ def makeLinuxX86System(
             )
         )
 
-    # Reserve the last 16KiB of the 32-bit address space for the m5op interface
-    entries.append(X86E820Entry(addr=0xFFFF0000, size="64KiB", range_type=2))
+    # Reserve the last 16kB of the 32-bit address space for the m5op interface
+    entries.append(X86E820Entry(addr=0xFFFF0000, size="64kB", range_type=2))
 
-    # In case the physical memory is greater than 3GiB, we split it into two
+    # In case the physical memory is greater than 3GB, we split it into two
     # parts and add a separate e820 entry for the second part.  This entry
     # starts at 0x100000000,  which is the first address after the space
     # reserved for devices.

configs/common/FileSystemConfig.py

@@ -36,31 +36,18 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import getpass
-import operator
-import os
-import platform
-from functools import reduce
-from os import (
-    access,
-    getpid,
-    listdir,
-    makedirs,
-    mkdir,
-    stat,
-)
-from os.path import isdir
-from os.path import join as joinpath
-from pwd import getpwuid
-from shutil import (
-    copyfile,
-    rmtree,
-)
-
 import m5
 from m5.objects import *
 from m5.util.convert import *
 
+from functools import reduce
+import operator, os, platform, getpass
+from os import mkdir, makedirs, getpid, listdir, stat, access
+from pwd import getpwuid
+from os.path import join as joinpath
+from os.path import isdir
+from shutil import rmtree, copyfile
+
 
 def hex_mask(terms):
     dec_mask = reduce(operator.or_, [2**i for i in terms], 0)
@@ -202,7 +189,7 @@ def register_node(cpu_list, mem, node_number):
     file_append((nodedir, "cpumap"), hex_mask(cpu_list))
     file_append(
         (nodedir, "meminfo"),
-        "Node %d MemTotal: %dKiB"
+        "Node %d MemTotal: %dkB"
         % (node_number, toMemorySize(str(mem)) / kibi),
     )
 

configs/common/GPUTLBConfig.py

@@ -36,6 +36,7 @@ from m5.objects import *
 
 
 def TLB_constructor(options, level, gpu_ctrl=None, full_system=False):
+
     if full_system:
         constructor_call = (
             "VegaGPUTLB(\
@@ -70,6 +71,7 @@ def TLB_constructor(options, level, gpu_ctrl=None, full_system=False):
 
 
 def Coalescer_constructor(options, level, full_system):
+
     if full_system:
         constructor_call = (
             "VegaTLBCoalescer(probesPerCycle = \

configs/common/GPUTLBOptions.py

@@ -29,6 +29,7 @@
 
 
 def tlb_options(parser):
+
     # ===================================================================
     # TLB Configuration
     # ===================================================================
@@ -44,8 +45,8 @@ def tlb_options(parser):
     #   L1 TLB Options (D-TLB, I-TLB, Dispatcher-TLB)
     # ===================================================================
 
-    parser.add_argument("--L1TLBentries", type=int, default="64")
-    parser.add_argument("--L1TLBassoc", type=int, default="64")
+    parser.add_argument("--L1TLBentries", type=int, default="32")
+    parser.add_argument("--L1TLBassoc", type=int, default="32")
     parser.add_argument(
         "--L1AccessLatency",
         type=int,
@@ -68,7 +69,7 @@ def tlb_options(parser):
     # ===================================================================
 
     parser.add_argument("--L2TLBentries", type=int, default="4096")
-    parser.add_argument("--L2TLBassoc", type=int, default="64")
+    parser.add_argument("--L2TLBassoc", type=int, default="32")
     parser.add_argument(
         "--L2AccessLatency",
         type=int,
@@ -90,7 +91,7 @@ def tlb_options(parser):
     # ===================================================================
 
     parser.add_argument("--L3TLBentries", type=int, default="8192")
-    parser.add_argument("--L3TLBassoc", type=int, default="64")
+    parser.add_argument("--L3TLBassoc", type=int, default="32")
     parser.add_argument(
         "--L3AccessLatency",
         type=int,

configs/common/HMC.py

@@ -300,10 +300,10 @@ def add_options(parser):
     # address range for each of the serial links
     parser.add_argument(
         "--serial-link-addr-range",
-        default="1GiB",
+        default="1GB",
         type=str,
         help="memory range for each of the serial links.\
-                        Default: 1GiB",
+                        Default: 1GB",
     )
 
     # *****************************PERFORMANCE MONITORING*********************
@@ -390,10 +390,10 @@ def add_options(parser):
     # HMC device - vault capacity or size
     parser.add_argument(
         "--hmc-dev-vault-size",
-        default="256MiB",
+        default="256MB",
         type=str,
         help="vault storage capacity in bytes. Default:\
-                        256MiB",
+                        256MB",
     )
     parser.add_argument(
         "--mem-type",
@@ -430,6 +430,7 @@ def add_options(parser):
 
 # configure HMC host controller
 def config_hmc_host_ctrl(opt, system):
+
     # create HMC host controller
     system.hmc_host = SubSystem()
 
@@ -532,6 +533,7 @@ def config_hmc_host_ctrl(opt, system):
 
 # Create an HMC device
 def config_hmc_dev(opt, system, hmc_host):
+
     # create HMC device
     system.hmc_dev = SubSystem()
 
@@ -568,9 +570,9 @@ def config_hmc_dev(opt, system, hmc_host):
     # Attach 4 serial link to 4 crossbar/s
     for i in range(opt.num_serial_links):
         if opt.enable_link_monitor:
-            system.hmc_host.seriallink[i].mem_side_port = (
-                system.hmc_dev.lmonitor[i].cpu_side_port
-            )
+            system.hmc_host.seriallink[
+                i
+            ].mem_side_port = system.hmc_dev.lmonitor[i].cpu_side_port
             system.hmc_dev.lmonitor[i].mem_side_port = system.hmc_dev.xbar[
                 i
             ].cpu_side_ports
@@ -613,12 +615,14 @@ def config_hmc_dev(opt, system, hmc_host):
                     ]
 
                     # Connect the bridge between corssbars
-                    system.hmc_dev.xbar[i].mem_side_ports = (
-                        system.hmc_dev.buffers[index].cpu_side_port
-                    )
-                    system.hmc_dev.buffers[index].mem_side_port = (
-                        system.hmc_dev.xbar[j].cpu_side_ports
-                    )
+                    system.hmc_dev.xbar[
+                        i
+                    ].mem_side_ports = system.hmc_dev.buffers[
+                        index
+                    ].cpu_side_port
+                    system.hmc_dev.buffers[
+                        index
+                    ].mem_side_port = system.hmc_dev.xbar[j].cpu_side_ports
                 else:
                     # Don't connect the xbar to itself
                     pass
@@ -627,49 +631,49 @@ def config_hmc_dev(opt, system, hmc_host):
     # can only direct traffic to it local vaults
     if opt.arch == "mixed":
         system.hmc_dev.buffer30 = Bridge(ranges=system.mem_ranges[0:4])
-        system.hmc_dev.xbar[3].mem_side_ports = (
-            system.hmc_dev.buffer30.cpu_side_port
-        )
+        system.hmc_dev.xbar[
+            3
+        ].mem_side_ports = system.hmc_dev.buffer30.cpu_side_port
         system.hmc_dev.buffer30.mem_side_port = system.hmc_dev.xbar[
             0
         ].cpu_side_ports
 
         system.hmc_dev.buffer31 = Bridge(ranges=system.mem_ranges[4:8])
-        system.hmc_dev.xbar[3].mem_side_ports = (
-            system.hmc_dev.buffer31.cpu_side_port
-        )
+        system.hmc_dev.xbar[
+            3
+        ].mem_side_ports = system.hmc_dev.buffer31.cpu_side_port
         system.hmc_dev.buffer31.mem_side_port = system.hmc_dev.xbar[
             1
         ].cpu_side_ports
 
         system.hmc_dev.buffer32 = Bridge(ranges=system.mem_ranges[8:12])
-        system.hmc_dev.xbar[3].mem_side_ports = (
-            system.hmc_dev.buffer32.cpu_side_port
-        )
+        system.hmc_dev.xbar[
+            3
+        ].mem_side_ports = system.hmc_dev.buffer32.cpu_side_port
         system.hmc_dev.buffer32.mem_side_port = system.hmc_dev.xbar[
             2
         ].cpu_side_ports
 
         system.hmc_dev.buffer20 = Bridge(ranges=system.mem_ranges[0:4])
-        system.hmc_dev.xbar[2].mem_side_ports = (
-            system.hmc_dev.buffer20.cpu_side_port
-        )
+        system.hmc_dev.xbar[
+            2
+        ].mem_side_ports = system.hmc_dev.buffer20.cpu_side_port
         system.hmc_dev.buffer20.mem_side_port = system.hmc_dev.xbar[
             0
         ].cpu_side_ports
 
         system.hmc_dev.buffer21 = Bridge(ranges=system.mem_ranges[4:8])
-        system.hmc_dev.xbar[2].mem_side_ports = (
-            system.hmc_dev.buffer21.cpu_side_port
-        )
+        system.hmc_dev.xbar[
+            2
+        ].mem_side_ports = system.hmc_dev.buffer21.cpu_side_port
         system.hmc_dev.buffer21.mem_side_port = system.hmc_dev.xbar[
             1
         ].cpu_side_ports
 
         system.hmc_dev.buffer23 = Bridge(ranges=system.mem_ranges[12:16])
-        system.hmc_dev.xbar[2].mem_side_ports = (
-            system.hmc_dev.buffer23.cpu_side_port
-        )
+        system.hmc_dev.xbar[
+            2
+        ].mem_side_ports = system.hmc_dev.buffer23.cpu_side_port
         system.hmc_dev.buffer23.mem_side_port = system.hmc_dev.xbar[
             3
         ].cpu_side_ports

configs/common/MemConfig.py

@@ -33,17 +33,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from common import (
-    HMC,
-    ObjectList,
-)
-
 import m5.objects
+from common import ObjectList
+from common import HMC
 
 
 def create_mem_intf(intf, r, i, intlv_bits, intlv_size, xor_low_bit):
     """
-    Helper function for creating a single memory controller from the given
+    Helper function for creating a single memoy controller from the given
     options.  This function is invoked multiple times in config_mem function
     to create an array of controllers.
     """
@@ -177,7 +174,6 @@ def config_mem(options, system):
     nbr_mem_ctrls = opt_mem_channels
 
     import math
-
     from m5.util import fatal
 
     intlv_bits = int(math.log(nbr_mem_ctrls, 2))

configs/common/ObjectList.py

@@ -34,18 +34,15 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from gem5.runtime import get_supported_isas
+import m5.objects
+import m5.internal.params
 import inspect
 import sys
 from textwrap import TextWrapper
 
-import m5.internal.params
-import m5.objects
 
-from gem5.isas import ISA
-from gem5.runtime import get_supported_isas
-
-
-class ObjectList:
+class ObjectList(object):
     """Creates a list of objects that are sub-classes of a given class."""
 
     def _is_obj_class(self, cls):
@@ -89,7 +86,7 @@ class ObjectList:
                     print(line)
 
         if self._aliases:
-            print(r"\Aliases:")
+            print("\Aliases:")
             for alias, target in list(self._aliases.items()):
                 print(f"\t{alias} => {target}")
 
@@ -130,14 +127,14 @@ class CPUList(ObjectList):
         # We can't use the normal inspect.isclass because the ParamFactory
         # and ProxyFactory classes have a tendency to confuse it.
         try:
-            return super()._is_obj_class(cls) and not issubclass(
+            return super(CPUList, self)._is_obj_class(cls) and not issubclass(
                 cls, m5.objects.CheckerCPU
             )
         except (TypeError, AttributeError):
             return False
 
     def _add_objects(self):
-        super()._add_objects()
+        super(CPUList, self)._add_objects()
 
         from importlib import import_module
 
@@ -160,27 +157,6 @@ class CPUList(ObjectList):
                 ):
                     self._sub_classes[name] = cls
 
-    def get_isa(self, name: str) -> ISA:
-        """For a given CPU (string representation) determine the ISA of the
-        CPU."""
-
-        cls = self.get(name)
-
-        if hasattr(m5.objects, "X86CPU") and issubclass(
-            cls, m5.objects.X86CPU
-        ):
-            return ISA.X86
-        elif hasattr(m5.objects, "ArmCPU") and issubclass(
-            cls, m5.objects.ArmCPU
-        ):
-            return ISA.ARM
-        elif hasattr(m5.objects, "RiscvCPU") and issubclass(
-            cls, m5.objects.RiscvCPU
-        ):
-            return ISA.RISCV
-        else:
-            raise ValueError("Unable to determine CPU ISA.")
-
 
 class EnumList(ObjectList):
     """Creates a list of possible values for a given enum class."""
@@ -188,7 +164,7 @@ class EnumList(ObjectList):
     def _add_objects(self):
         """Add all enum values to the ObjectList"""
         self._sub_classes = {}
-        for key, value in list(self.base_cls.__members__.items()):
+        for (key, value) in list(self.base_cls.__members__.items()):
             # All Enums have a value Num_NAME at the end which we
             # do not want to include
             if not key.startswith("Num_"):
@@ -228,4 +204,3 @@ def _subclass_tester(name):
 
 is_kvm_cpu = _subclass_tester("BaseKvmCPU")
 is_noncaching_cpu = _subclass_tester("NonCachingSimpleCPU")
-is_o3_cpu = _subclass_tester("BaseO3CPU")

configs/common/Options.py

@@ -37,20 +37,13 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import argparse
-from typing import Optional
-
-from common import (
-    CpuConfig,
-    ObjectList,
-)
-from common.Benchmarks import *
 
 import m5
 from m5.defines import buildEnv
 from m5.objects import *
 
-from gem5.isas import ISA
-from gem5.runtime import get_supported_isas
+from common.Benchmarks import *
+from common import ObjectList
 
 vio_9p_help = """\
 Enable the Virtio 9P device and set the path to share. The default 9p path is
@@ -155,7 +148,7 @@ def addNoISAOptions(parser):
         "--mem-size",
         action="store",
         type=str,
-        default="512MiB",
+        default="512MB",
         help="Specify the physical memory size (single memory)",
     )
     parser.add_argument(
@@ -188,10 +181,10 @@ def addNoISAOptions(parser):
     parser.add_argument("--num-dirs", type=int, default=1)
     parser.add_argument("--num-l2caches", type=int, default=1)
     parser.add_argument("--num-l3caches", type=int, default=1)
-    parser.add_argument("--l1d_size", type=str, default="64KiB")
-    parser.add_argument("--l1i_size", type=str, default="32KiB")
-    parser.add_argument("--l2_size", type=str, default="2MiB")
-    parser.add_argument("--l3_size", type=str, default="16MiB")
+    parser.add_argument("--l1d_size", type=str, default="64kB")
+    parser.add_argument("--l1i_size", type=str, default="32kB")
+    parser.add_argument("--l2_size", type=str, default="2MB")
+    parser.add_argument("--l3_size", type=str, default="16MB")
     parser.add_argument("--l1d_assoc", type=int, default=2)
     parser.add_argument("--l1i_assoc", type=int, default=2)
     parser.add_argument("--l2_assoc", type=int, default=8)
@@ -244,13 +237,9 @@ def addNoISAOptions(parser):
 # Add common options that assume a non-NULL ISA.
 
 
-def addCommonOptions(parser, default_isa: Optional[ISA] = None):
+def addCommonOptions(parser):
     # start by adding the base options that do not assume an ISA
     addNoISAOptions(parser)
-    if default_isa is None:
-        isa = list(get_supported_isas())[0]
-    else:
-        isa = default_isa
 
     # system options
     parser.add_argument(
@@ -261,7 +250,7 @@ def addCommonOptions(parser, default_isa: Optional[ISA] = None):
     )
     parser.add_argument(
         "--cpu-type",
-        default=CpuConfig.isa_string_map[isa] + "AtomicSimpleCPU",
+        default="AtomicSimpleCPU",
         choices=ObjectList.cpu_list.get_names(),
         help="type of cpu to run with",
     )
@@ -592,7 +581,7 @@ def addCommonOptions(parser, default_isa: Optional[ISA] = None):
     parser.add_argument(
         "--restore-with-cpu",
         action="store",
-        default=CpuConfig.isa_string_map[isa] + "AtomicSimpleCPU",
+        default="AtomicSimpleCPU",
         choices=ObjectList.cpu_list.get_names(),
         help="cpu type for restoring from a checkpoint",
     )
@@ -795,20 +784,12 @@ def addFSOptions(parser):
         "files in the gem5 output directory",
     )
 
-    if buildEnv["USE_ARM_ISA"] or buildEnv["USE_RISCV_ISA"]:
+    if buildEnv["USE_ARM_ISA"]:
         parser.add_argument(
             "--bare-metal",
             action="store_true",
             help="Provide the raw system without the linux specific bits",
         )
-        parser.add_argument(
-            "--dtb-filename",
-            action="store",
-            type=str,
-            help="Specifies device tree blob file to use with device-tree-"
-            "enabled kernels",
-        )
-    if buildEnv["USE_ARM_ISA"]:
         parser.add_argument(
             "--list-machine-types",
             action=ListPlatform,
@@ -821,6 +802,13 @@ def addFSOptions(parser):
             choices=ObjectList.platform_list.get_names(),
             default="VExpress_GEM5_V1",
         )
+        parser.add_argument(
+            "--dtb-filename",
+            action="store",
+            type=str,
+            help="Specifies device tree blob file to use with device-tree-"
+            "enabled kernels",
+        )
         parser.add_argument(
             "--enable-context-switch-stats-dump",
             action="store_true",

configs/common/SimpleOpts.py

@@ -1,3 +1,4 @@
+# -*- coding: utf-8 -*-
 # Copyright (c) 2015 Jason Power
 # All rights reserved.
 #
@@ -34,12 +35,12 @@ from each class instead of only from the configuration script.
 # Module-level variable to track if we've called the parse_args function yet
 called_parse_args = False
 
-# import the argument parser
-from argparse import ArgumentParser
-
 # For fatal
 import m5
 
+# import the argument parser
+from argparse import ArgumentParser
+
 # add the args we want to be able to control from the command line
 parser = ArgumentParser()
 

configs/common/Simulation.py

@@ -41,10 +41,8 @@ import sys
 from os import getcwd
 from os.path import join as joinpath
 
-from common import (
-    CpuConfig,
-    ObjectList,
-)
+from common import CpuConfig
+from common import ObjectList
 
 import m5
 from m5.defines import buildEnv
@@ -81,10 +79,7 @@ def setCPUClass(options):
             TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu)
     elif options.fast_forward:
         CPUClass = TmpClass
-        CPUISA = ObjectList.cpu_list.get_isa(options.cpu_type)
-        TmpClass = getCPUClass(
-            CpuConfig.isa_string_map[CPUISA] + "AtomicSimpleCPU"
-        )
+        TmpClass = AtomicSimpleCPU
         test_mem_mode = "atomic"
 
     # Ruby only supports atomic accesses in noncaching mode
@@ -133,12 +128,9 @@ def findCptDir(options, cptdir, testsys):
     the appropriate directory.
     """
 
-    import re
+    from os.path import isdir, exists
     from os import listdir
-    from os.path import (
-        exists,
-        isdir,
-    )
+    import re
 
     if not isdir(cptdir):
         fatal("checkpoint dir %s does not exist!", cptdir)
@@ -161,8 +153,8 @@ def findCptDir(options, cptdir, testsys):
         # Assumes that the checkpoint dir names are formatted as follows:
         dirs = listdir(cptdir)
         expr = re.compile(
-            r"cpt\.simpoint_(\d+)_inst_(\d+)"
-            + r"_weight_([\d\.e\-]+)_interval_(\d+)_warmup_(\d+)"
+            "cpt\.simpoint_(\d+)_inst_(\d+)"
+            + "_weight_([\d\.e\-]+)_interval_(\d+)_warmup_(\d+)"
         )
         cpts = []
         for dir in dirs:
@@ -198,7 +190,7 @@ def findCptDir(options, cptdir, testsys):
 
     else:
         dirs = listdir(cptdir)
-        expr = re.compile(r"cpt\.([0-9]+)")
+        expr = re.compile("cpt\.([0-9]+)")
         cpts = []
         for dir in dirs:
             match = expr.match(dir)
@@ -333,7 +325,7 @@ def parseSimpointAnalysisFile(options, testsys):
         line = simpoint_file.readline()
         if not line:
             break
-        m = re.match(r"(\d+)\s+(\d+)", line)
+        m = re.match("(\d+)\s+(\d+)", line)
         if m:
             interval = int(m.group(1))
         else:
@@ -342,7 +334,7 @@ def parseSimpointAnalysisFile(options, testsys):
         line = weight_file.readline()
         if not line:
             fatal("not enough lines in simpoint weight file!")
-        m = re.match(r"([0-9\.e\-]+)\s+(\d+)", line)
+        m = re.match("([0-9\.e\-]+)\s+(\d+)", line)
         if m:
             weight = float(m.group(1))
         else:
@@ -541,9 +533,9 @@ def run(options, root, testsys, cpu_class):
                 IndirectBPClass = ObjectList.indirect_bp_list.get(
                     options.indirect_bp_type
                 )
-                switch_cpus[i].branchPred.indirectBranchPred = (
-                    IndirectBPClass()
-                )
+                switch_cpus[
+                    i
+                ].branchPred.indirectBranchPred = IndirectBPClass()
             switch_cpus[i].createThreads()
 
         # If elastic tracing is enabled attach the elastic trace probe
@@ -779,6 +771,7 @@ def run(options, root, testsys, cpu_class):
     if (
         options.take_checkpoints or options.take_simpoint_checkpoints
     ) and options.checkpoint_restore:
+
         if m5.options.outdir:
             cptdir = m5.options.outdir
         else:

configs/common/SysPaths.py

@@ -24,14 +24,13 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import os
-import sys
+import os, sys
 
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
 
 
-class PathSearchFunc:
+class PathSearchFunc(object):
     _sys_paths = None
     environment_variable = "M5_PATH"
 
@@ -59,7 +58,7 @@ class PathSearchFunc:
                 paths = list(filter(os.path.isdir, paths))
 
                 if not paths:
-                    raise OSError(
+                    raise IOError(
                         "Can't find system files directory, "
                         "check your {} environment variable".format(
                             self.environment_variable
@@ -73,7 +72,7 @@ class PathSearchFunc:
             try:
                 return next(p for p in paths if os.path.exists(p))
             except StopIteration:
-                raise OSError(
+                raise IOError(
                     f"Can't find file '{filepath}' on {self.environment_variable}."
                 )
 

configs/common/cores/arm/HPI.py

@@ -44,7 +44,6 @@ at: http://www.arm.com/ResearchEnablement/SystemModeling
 
 from m5.objects import *
 
-
 # Simple function to allow a string of [01x_] to be converted into a
 # mask and value for use with MinorFUTiming
 def make_implicant(implicant_string):
@@ -1680,23 +1679,7 @@ class HPI_MMU(ArmMMU):
     dtb = ArmTLB(entry_type="data", size=256)
 
 
-class HPI_BTB(SimpleBTB):
-    numEntries = 128
-    tagBits = 18
-    associativity = 1
-    instShiftAmt = 2
-    btbReplPolicy = LRURP()
-    btbIndexingPolicy = BTBSetAssociative(
-        num_entries=Parent.numEntries,
-        set_shift=Parent.instShiftAmt,
-        assoc=Parent.associativity,
-        tag_bits=Parent.tagBits,
-    )
-
-
 class HPI_BP(TournamentBP):
-    btb = HPI_BTB()
-    ras = ReturnAddrStack(numEntries=8)
     localPredictorSize = 64
     localCtrBits = 2
     localHistoryTableSize = 64
@@ -1704,6 +1687,9 @@ class HPI_BP(TournamentBP):
     globalCtrBits = 2
     choicePredictorSize = 1024
     choiceCtrBits = 2
+    BTBEntries = 128
+    BTBTagSize = 18
+    RASSize = 8
     instShiftAmt = 2
 
 
@@ -1713,7 +1699,7 @@ class HPI_ICache(Cache):
     response_latency = 1
     mshrs = 2
     tgts_per_mshr = 8
-    size = "32KiB"
+    size = "32kB"
     assoc = 2
     # No prefetcher, this is handled by the core
 
@@ -1724,7 +1710,7 @@ class HPI_DCache(Cache):
     response_latency = 1
     mshrs = 4
     tgts_per_mshr = 8
-    size = "32KiB"
+    size = "32kB"
     assoc = 4
     write_buffers = 4
     prefetcher = StridePrefetcher(queue_size=4, degree=4)
@@ -1736,7 +1722,7 @@ class HPI_L2(Cache):
     response_latency = 5
     mshrs = 4
     tgts_per_mshr = 8
-    size = "1024KiB"
+    size = "1024kB"
     assoc = 16
     write_buffers = 16
     # prefetcher FIXME

configs/common/cores/arm/O3_ARM_Etrace.py

@@ -1,60 +0,0 @@
-# Copyright (c) 2012, 2017-2018, 2023 Arm Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder.  You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from m5.objects import *
-
-from .O3_ARM_v7a import O3_ARM_v7a_3
-
-
-# O3_ARM_v7a_3 adapted to generate elastic traces
-class O3_ARM_v7a_3_Etrace(O3_ARM_v7a_3):
-    # Make the number of entries in the ROB, LQ and SQ very
-    # large so that there are no stalls due to resource
-    # limitation as such stalls will get captured in the trace
-    # as compute delay. For replay, ROB, LQ and SQ sizes are
-    # modelled in the Trace CPU.
-    numROBEntries = 512
-    LQEntries = 128
-    SQEntries = 128
-
-    def attach_probe_listener(self, inst_trace_file, data_trace_file):
-        # Attach the elastic trace probe listener. Set the protobuf trace
-        # file names. Set the dependency window size equal to the cpu it
-        # is attached to.
-        self.traceListener = m5.objects.ElasticTrace(
-            instFetchTraceFile=inst_trace_file,
-            dataDepTraceFile=data_trace_file,
-            depWindowSize=3 * self.numROBEntries,
-        )

configs/common/cores/arm/O3_ARM_v7a.py

@@ -26,7 +26,6 @@
 
 from m5.objects import *
 
-
 # Simple ALU Instructions have a latency of 1
 class O3_ARM_v7a_Simple_Int(FUDesc):
     opList = [OpDesc(opClass="IntAlu", opLat=1)]
@@ -108,28 +107,15 @@ class O3_ARM_v7a_FUP(FUPool):
     ]
 
 
-class O3_ARM_v7a_BTB(SimpleBTB):
-    numEntries = 2048
-    tagBits = 18
-    associativity = 1
-    instShiftAmt = 2
-    btbReplPolicy = LRURP()
-    btbIndexingPolicy = BTBSetAssociative(
-        num_entries=Parent.numEntries,
-        set_shift=Parent.instShiftAmt,
-        assoc=Parent.associativity,
-        tag_bits=Parent.tagBits,
-    )
-
-
 # Bi-Mode Branch Predictor
 class O3_ARM_v7a_BP(BiModeBP):
-    btb = O3_ARM_v7a_BTB()
-    ras = ReturnAddrStack(numEntries=16)
     globalPredictorSize = 8192
     globalCtrBits = 2
     choicePredictorSize = 8192
     choiceCtrBits = 2
+    BTBEntries = 2048
+    BTBTagSize = 18
+    RASSize = 16
     instShiftAmt = 2
 
 
@@ -185,7 +171,7 @@ class O3_ARM_v7a_ICache(Cache):
     response_latency = 1
     mshrs = 2
     tgts_per_mshr = 8
-    size = "32KiB"
+    size = "32kB"
     assoc = 2
     is_read_only = True
     # Writeback clean lines as well
@@ -199,7 +185,7 @@ class O3_ARM_v7a_DCache(Cache):
     response_latency = 2
     mshrs = 6
     tgts_per_mshr = 8
-    size = "32KiB"
+    size = "32kB"
     assoc = 2
     write_buffers = 16
     # Consider the L2 a victim cache also for clean lines
@@ -213,11 +199,12 @@ class O3_ARM_v7aL2(Cache):
     response_latency = 12
     mshrs = 16
     tgts_per_mshr = 8
-    size = "1MiB"
+    size = "1MB"
     assoc = 16
     write_buffers = 8
+    prefetch_on_access = True
     clusivity = "mostly_excl"
     # Simple stride prefetcher
-    prefetcher = StridePrefetcher(degree=8, latency=1, prefetch_on_access=True)
+    prefetcher = StridePrefetcher(degree=8, latency=1)
     tags = BaseSetAssoc()
     replacement_policy = RandomRP()

configs/common/cores/arm/__init__.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from importlib import import_module
 from pkgutil import iter_modules
+from importlib import import_module
 
 _cpu_modules = [name for _, name, ispkg in iter_modules(__path__) if not ispkg]
 

configs/common/cores/arm/ex5_LITTLE.py

@@ -31,7 +31,6 @@ from m5.objects import *
 #                ex5 LITTLE core (based on the ARM Cortex-A7)
 # -----------------------------------------------------------------------
 
-
 # Simple ALU Instructions have a latency of 3
 class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
     opList = [OpDesc(opClass="IntAlu", opLat=4)]
@@ -124,7 +123,7 @@ class L1Cache(Cache):
 
 class L1I(L1Cache):
     mshrs = 2
-    size = "32KiB"
+    size = "32kB"
     assoc = 2
     is_read_only = True
     tgts_per_mshr = 20
@@ -132,7 +131,7 @@ class L1I(L1Cache):
 
 class L1D(L1Cache):
     mshrs = 4
-    size = "32KiB"
+    size = "32kB"
     assoc = 4
     write_buffers = 4
 
@@ -144,11 +143,12 @@ class L2(Cache):
     response_latency = 9
     mshrs = 8
     tgts_per_mshr = 12
-    size = "512KiB"
+    size = "512kB"
     assoc = 8
     write_buffers = 16
+    prefetch_on_access = True
     clusivity = "mostly_excl"
     # Simple stride prefetcher
-    prefetcher = StridePrefetcher(degree=1, latency=1, prefetch_on_access=True)
+    prefetcher = StridePrefetcher(degree=1, latency=1)
     tags = BaseSetAssoc()
     replacement_policy = RandomRP()

configs/common/cores/arm/ex5_big.py

@@ -31,7 +31,6 @@ from m5.objects import *
 #                ex5 big core (based on the ARM Cortex-A15)
 # -----------------------------------------------------------------------
 
-
 # Simple ALU Instructions have a latency of 1
 class ex5_big_Simple_Int(FUDesc):
     opList = [OpDesc(opClass="IntAlu", opLat=1)]
@@ -105,28 +104,15 @@ class ex5_big_FUP(FUPool):
     ]
 
 
-class ex5_big_BTB(SimpleBTB):
-    numEntries = 4096
-    tagBits = 18
-    associativity = 1
-    instShiftAmt = 2
-    btbReplPolicy = LRURP()
-    btbIndexingPolicy = BTBSetAssociative(
-        num_entries=Parent.numEntries,
-        set_shift=Parent.instShiftAmt,
-        assoc=Parent.associativity,
-        tag_bits=Parent.tagBits,
-    )
-
-
 # Bi-Mode Branch Predictor
 class ex5_big_BP(BiModeBP):
-    btb = ex5_big_BTB()
-    ras = ReturnAddrStack(numEntries=48)
     globalPredictorSize = 4096
     globalCtrBits = 2
     choicePredictorSize = 1024
     choiceCtrBits = 3
+    BTBEntries = 4096
+    BTBTagSize = 18
+    RASSize = 48
     instShiftAmt = 2
 
 
@@ -186,7 +172,7 @@ class L1Cache(Cache):
 # Instruction Cache
 class L1I(L1Cache):
     mshrs = 2
-    size = "32KiB"
+    size = "32kB"
     assoc = 2
     is_read_only = True
 
@@ -194,7 +180,7 @@ class L1I(L1Cache):
 # Data Cache
 class L1D(L1Cache):
     mshrs = 6
-    size = "32KiB"
+    size = "32kB"
     assoc = 2
     write_buffers = 16
 
@@ -206,11 +192,12 @@ class L2(Cache):
     response_latency = 15
     mshrs = 16
     tgts_per_mshr = 8
-    size = "2MiB"
+    size = "2MB"
     assoc = 16
     write_buffers = 8
+    prefetch_on_access = True
     clusivity = "mostly_excl"
     # Simple stride prefetcher
-    prefetcher = StridePrefetcher(degree=8, latency=1, prefetch_on_access=True)
+    prefetcher = StridePrefetcher(degree=8, latency=1)
     tags = BaseSetAssoc()
     replacement_policy = RandomRP()

configs/common/cpu2000.py

@@ -26,15 +26,8 @@
 
 import os
 import sys
-from os.path import (
-    basename,
-    exists,
-    isdir,
-    isfile,
-    islink,
-)
-from os.path import join as joinpath
-from os.path import normpath
+from os.path import basename, exists, join as joinpath, normpath
+from os.path import isdir, isfile, islink
 
 spec_dist = os.environ.get("M5_CPU2000", "/dist/m5/cpu2000")
 
@@ -78,7 +71,7 @@ def copyfiles(srcdir, dstdir):
         os.symlink(".", outlink)
 
 
-class Benchmark:
+class Benchmark(object):
     def __init__(self, isa, os, input_set):
         if not hasattr(self.__class__, "name"):
             self.name = self.__class__.__name__
@@ -884,7 +877,7 @@ class vortex(Benchmark):
         else:
             raise AttributeError(f"unknown ISA {isa}")
 
-        super().__init__(isa, os, input_set)
+        super(vortex, self).__init__(isa, os, input_set)
 
     def test(self, isa, os):
         self.args = [f"{self.endian}.raw"]

configs/deprecated/example/fs.py

@@ -45,30 +45,25 @@ import sys
 import m5
 from m5.defines import buildEnv
 from m5.objects import *
-from m5.util import (
-    addToPath,
-    fatal,
-    warn,
-)
+from m5.util import addToPath, fatal, warn
 from m5.util.fdthelper import *
-
 from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 addToPath("../../")
 
-from common import (
-    CacheConfig,
-    CpuConfig,
-    MemConfig,
-    ObjectList,
-    Options,
-    Simulation,
-)
-from common.Benchmarks import *
-from common.Caches import *
+from ruby import Ruby
+
 from common.FSConfig import *
 from common.SysPaths import *
-from ruby import Ruby
+from common.Benchmarks import *
+from common import Simulation
+from common import CacheConfig
+from common import CpuConfig
+from common import MemConfig
+from common import ObjectList
+from common.Caches import *
+from common import Options
 
 
 def cmd_line_template():
@@ -85,8 +80,9 @@ def cmd_line_template():
     return None
 
 
-def build_test_system(np, isa: ISA):
+def build_test_system(np):
     cmdline = cmd_line_template()
+    isa = get_runtime_isa()
     if isa == ISA.MIPS:
         test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
     elif isa == ISA.SPARC:
@@ -168,7 +164,7 @@ def build_test_system(np, isa: ISA):
         # assuming that there is just one such port.
         test_sys.iobus.mem_side_ports = test_sys.ruby._io_port.in_ports
 
-        for i, cpu in enumerate(test_sys.cpu):
+        for (i, cpu) in enumerate(test_sys.cpu):
             #
             # Tie the cpu ports to the correct ruby system ports
             #
@@ -213,9 +209,9 @@ def build_test_system(np, isa: ISA):
                     IndirectBPClass = ObjectList.indirect_bp_list.get(
                         args.indirect_bp_type
                     )
-                    test_sys.cpu[i].branchPred.indirectBranchPred = (
-                        IndirectBPClass()
-                    )
+                    test_sys.cpu[
+                        i
+                    ].branchPred.indirectBranchPred = IndirectBPClass()
             test_sys.cpu[i].createThreads()
 
         # If elastic tracing is enabled when not restoring from checkpoint and
@@ -382,8 +378,7 @@ else:
 
 np = args.num_cpus
 
-isa = ObjectList.cpu_list.get_isa(args.cpu_type)
-test_sys = build_test_system(np, isa)
+test_sys = build_test_system(np)
 
 if len(bm) == 2:
     drive_sys = build_drive_system(np)

configs/deprecated/example/se.py

@@ -41,35 +41,30 @@
 # "m5 test.py"
 
 import argparse
-import os
 import sys
+import os
 
 import m5
 from m5.defines import buildEnv
 from m5.objects import *
 from m5.params import NULL
-from m5.util import (
-    addToPath,
-    fatal,
-    warn,
-)
-
+from m5.util import addToPath, fatal, warn
 from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 addToPath("../../")
 
-from common import (
-    CacheConfig,
-    CpuConfig,
-    MemConfig,
-    ObjectList,
-    Options,
-    Simulation,
-)
+from ruby import Ruby
+
+from common import Options
+from common import Simulation
+from common import CacheConfig
+from common import CpuConfig
+from common import ObjectList
+from common import MemConfig
+from common.FileSystemConfig import config_filesystem
 from common.Caches import *
 from common.cpu2000 import *
-from common.FileSystemConfig import config_filesystem
-from ruby import Ruby
 
 
 def get_processes(args):
@@ -99,7 +94,7 @@ def get_processes(args):
         process.gid = os.getgid()
 
         if args.env:
-            with open(args.env) as f:
+            with open(args.env, "r") as f:
                 process.env = [line.rstrip() for line in f]
 
         if len(pargs) > idx:
@@ -118,8 +113,7 @@ def get_processes(args):
         idx += 1
 
     if args.smt:
-        cpu_type = ObjectList.cpu_list.get(args.cpu_type)
-        assert ObjectList.is_o3_cpu(cpu_type), "SMT requires an O3CPU"
+        assert args.cpu_type == "DerivO3CPU"
         return multiprocesses, idx
     else:
         return multiprocesses, 1
@@ -150,7 +144,7 @@ if args.bench:
 
     for app in apps:
         try:
-            if ObjectList.cpu_list.get_isa(args.cpu_type) == ISA.ARM:
+            if get_runtime_isa() == ISA.ARM:
                 exec(
                     "workload = %s('arm_%s', 'linux', '%s')"
                     % (app, args.arm_iset, args.spec_input)
@@ -165,7 +159,7 @@ if args.bench:
             multiprocesses.append(workload.makeProcess())
         except:
             print(
-                f"Unable to find workload for ISA: {app}",
+                f"Unable to find workload for {get_runtime_isa().name()}: {app}",
                 file=sys.stderr,
             )
             sys.exit(1)
@@ -224,7 +218,7 @@ for cpu in system.cpu:
 if ObjectList.is_kvm_cpu(CPUClass) or ObjectList.is_kvm_cpu(FutureClass):
     if buildEnv["USE_X86_ISA"]:
         system.kvm_vm = KvmVM()
-        system.m5ops_base = max(0xFFFF0000, Addr(args.mem_size).getValue())
+        system.m5ops_base = 0xFFFF0000
         for process in multiprocesses:
             process.useArchPT = True
             process.kvmInSE = True

configs/dist/sw.py

@@ -62,7 +62,7 @@ def build_switch(args):
         for i in range(args.dist_size)
     ]
 
-    for i, link in enumerate(switch.portlink):
+    for (i, link) in enumerate(switch.portlink):
         link.int0 = switch.interface[i]
 
     return switch

configs/dram/lat_mem_rd.py

@@ -33,20 +33,18 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import argparse
 import gzip
+import argparse
 import os
 
 import m5
 from m5.objects import *
-from m5.stats import periodicStatDump
 from m5.util import addToPath
+from m5.stats import periodicStatDump
 
 addToPath("../")
-from common import (
-    MemConfig,
-    ObjectList,
-)
+from common import ObjectList
+from common import MemConfig
 
 addToPath("../../util")
 import protolib
@@ -98,7 +96,7 @@ parser.add_argument(
     "--mem-size",
     action="store",
     type=str,
-    default="16MiB",
+    default="16MB",
     help="Specify the memory size",
 )
 parser.add_argument(
@@ -152,7 +150,6 @@ cfg_file = open(cfg_file_name, "w")
 burst_size = 64
 system.cache_line_size = burst_size
 
-
 # lazy version to check if an integer is a power of two
 def is_pow2(num):
     return num != 0 and ((num & (num - 1)) == 0)
@@ -161,7 +158,7 @@ def is_pow2(num):
 # assume we start every range at 0
 max_range = int(mem_range.end)
 
-# start at a size of 4 kibibyte, and go up till we hit the max, increase
+# start at a size of 4 kByte, and go up till we hit the max, increase
 # the step every time we hit a power of two
 min_range = 4096
 ranges = [min_range]
@@ -180,14 +177,13 @@ iterations = 2
 # do not pile up in the system, adjust if needed
 itt = 150 * 1000
 
-
 # for every data point, we create a trace containing a random address
 # sequence, so that we can play back the same sequence for warming and
 # the actual measurement
 def create_trace(filename, max_addr, burst_size, itt):
     try:
         proto_out = gzip.open(filename, "wb")
-    except OSError:
+    except IOError:
         print("Failed to open ", filename, " for writing")
         exit(-1)
 
@@ -280,7 +276,6 @@ system.tgen.port = system.monitor.cpu_side_port
 # basic to explore some of the options
 from common.Caches import *
 
-
 # a starting point for an L3 cache
 class L3Cache(Cache):
     assoc = 16
@@ -295,17 +290,17 @@ class L3Cache(Cache):
 
 # note that everything is in the same clock domain, 2.0 GHz as
 # specified above
-system.l1cache = L1_DCache(size="64KiB")
+system.l1cache = L1_DCache(size="64kB")
 system.monitor.mem_side_port = system.l1cache.cpu_side
 
-system.l2cache = L2Cache(size="512KiB", writeback_clean=True)
+system.l2cache = L2Cache(size="512kB", writeback_clean=True)
 system.l2cache.xbar = L2XBar()
 system.l1cache.mem_side = system.l2cache.xbar.cpu_side_ports
 system.l2cache.cpu_side = system.l2cache.xbar.mem_side_ports
 
 # make the L3 mostly exclusive, and correspondingly ensure that the L2
 # writes back also clean lines to the L3
-system.l3cache = L3Cache(size="4MiB", clusivity="mostly_excl")
+system.l3cache = L3Cache(size="4MB", clusivity="mostly_excl")
 system.l3cache.xbar = L2XBar()
 system.l2cache.mem_side = system.l3cache.xbar.cpu_side_ports
 system.l3cache.cpu_side = system.l3cache.xbar.mem_side_ports

configs/dram/low_power_sweep.py

@@ -37,15 +37,13 @@ import argparse
 
 import m5
 from m5.objects import *
-from m5.stats import periodicStatDump
 from m5.util import addToPath
+from m5.stats import periodicStatDump
 
 addToPath("../")
 
-from common import (
-    MemConfig,
-    ObjectList,
-)
+from common import ObjectList
+from common import MemConfig
 
 # This script aims at triggering low power state transitions in the DRAM
 # controller. The traffic generator is used in DRAM mode and traffic
@@ -116,8 +114,8 @@ system.clk_domain = SrcClockDomain(
     clock="2.0GHz", voltage_domain=VoltageDomain(voltage="1V")
 )
 
-# We are fine with 256 MiB memory for now.
-mem_range = AddrRange("256MiB")
+# We are fine with 256 MB memory for now.
+mem_range = AddrRange("256MB")
 # Start address is 0
 system.mem_ranges = [mem_range]
 

configs/dram/sweep.py

@@ -33,20 +33,18 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import argparse
 import math
+import argparse
 
 import m5
 from m5.objects import *
-from m5.stats import periodicStatDump
 from m5.util import addToPath
+from m5.stats import periodicStatDump
 
 addToPath("../")
 
-from common import (
-    MemConfig,
-    ObjectList,
-)
+from common import ObjectList
+from common import MemConfig
 
 # this script is helpful to sweep the efficiency of a specific memory
 # controller configuration, by varying the number of banks accessed,
@@ -108,8 +106,8 @@ system.clk_domain = SrcClockDomain(
     clock="2.0GHz", voltage_domain=VoltageDomain(voltage="1V")
 )
 
-# we are fine with 256 MiB memory for now
-mem_range = AddrRange("256MiB")
+# we are fine with 256 MB memory for now
+mem_range = AddrRange("256MB")
 system.mem_ranges = [mem_range]
 
 # do not worry about reserving space for the backing store

configs/example/apu_se.py

@@ -27,35 +27,29 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
-import argparse
-import getpass
+import argparse, os, re, getpass
+import math
 import glob
 import inspect
-import math
-import os
-import re
 
 import m5
 from m5.objects import *
 from m5.util import addToPath
-
 from gem5.isas import ISA
-from gem5.resources.resource import obtain_resource
-from gem5.runtime import get_supported_isas
+from gem5.runtime import get_runtime_isa
 
 addToPath("../")
 
-import hsaTopology
-from common import (
-    FileSystemConfig,
-    GPUTLBConfig,
-    GPUTLBOptions,
-    ObjectList,
-    Options,
-    Simulation,
-)
 from ruby import Ruby
 
+from common import Options
+from common import Simulation
+from common import GPUTLBOptions, GPUTLBConfig
+
+import hsaTopology
+from common import FileSystemConfig
+
+
 # Adding script options
 parser = argparse.ArgumentParser()
 Options.addCommonOptions(parser)
@@ -296,14 +290,6 @@ parser.add_argument(
     help="Latency for scalar responses from ruby to the cu.",
 )
 
-parser.add_argument(
-    "--memtime-latency",
-    type=int,
-    # Set to a default of 41 from micro-benchmarks
-    default=41,
-    help="Latency for memtimes in scalar memory pipeline.",
-)
-
 parser.add_argument("--TLB-prefetch", type=int, help="prefetch depth for TLBs")
 parser.add_argument(
     "--pf-type",
@@ -345,12 +331,6 @@ parser.add_argument(
     default="dynamic",
     help="register allocation policy (simple/dynamic)",
 )
-parser.add_argument(
-    "--register-file-cache-size",
-    type=int,
-    default=0,
-    help="number of registers in cache",
-)
 
 parser.add_argument(
     "--dgpu",
@@ -385,52 +365,11 @@ parser.add_argument(
 parser.add_argument(
     "--gfx-version",
     type=str,
-    default="gfx902",
+    default="gfx801",
     choices=GfxVersion.vals,
     help="Gfx version for gpuNote: gfx902 is not fully supported by ROCm",
 )
 
-parser.add_argument(
-    "--tcp-rp",
-    type=str,
-    default="TreePLRURP",
-    choices=ObjectList.rp_list.get_names(),
-    help="cache replacement policy" "policy for tcp",
-)
-
-parser.add_argument(
-    "--tcc-rp",
-    type=str,
-    default="TreePLRURP",
-    choices=ObjectList.rp_list.get_names(),
-    help="cache replacement policy" "policy for tcc",
-)
-
-# sqc rp both changes sqc rp and scalar cache rp
-parser.add_argument(
-    "--sqc-rp",
-    type=str,
-    default="TreePLRURP",
-    choices=ObjectList.rp_list.get_names(),
-    help="cache replacement policy" "policy for sqc",
-)
-
-parser.add_argument(
-    "--download-resource",
-    type=str,
-    default=None,
-    required=False,
-    help="Download this resources prior to simulation",
-)
-
-parser.add_argument(
-    "--download-dir",
-    type=str,
-    default=None,
-    required=False,
-    help="Download resources to this directory",
-)
-
 Ruby.define_options(parser)
 
 # add TLB options to the parser
@@ -438,17 +377,6 @@ GPUTLBOptions.tlb_options(parser)
 
 args = parser.parse_args()
 
-# Get the resource if specified.
-if args.download_resource:
-    resources = obtain_resource(
-        resource_id=args.download_resource,
-        resource_directory=args.download_dir,
-    )
-
-    # This line seems pointless but is actually what triggers the download.
-    resources.get_local_path()
-
-
 # The GPU cache coherence protocols only work with the backing store
 args.access_backing_store = True
 
@@ -466,8 +394,8 @@ if buildEnv["PROTOCOL"] == "None":
     fatal("GPU model requires ruby")
 
 # Currently the gpu model requires only timing or detailed CPU
-if not (args.cpu_type == "X86TimingSimpleCPU" or args.cpu_type == "X86O3CPU"):
-    fatal("GPU model requires X86TimingSimpleCPU or X86O3CPU.")
+if not (args.cpu_type == "TimingSimpleCPU" or args.cpu_type == "DerivO3CPU"):
+    fatal("GPU model requires TimingSimpleCPU or DerivO3CPU")
 
 # This file can support multiple compute units
 assert args.num_compute_units >= 1
@@ -496,7 +424,6 @@ print(
 # shader is the GPU
 shader = Shader(
     n_wf=args.wfs_per_simd,
-    cu_per_sqc=args.cu_per_sqc,
     clk_domain=SrcClockDomain(
         clock=args.gpu_clock,
         voltage_domain=VoltageDomain(voltage=args.gpu_voltage),
@@ -551,7 +478,6 @@ for i in range(n_cu):
             mem_resp_latency=args.mem_resp_latency,
             scalar_mem_req_latency=args.scalar_mem_req_latency,
             scalar_mem_resp_latency=args.scalar_mem_resp_latency,
-            memtime_latency=args.memtime_latency,
             localDataStore=LdsState(
                 banks=args.numLdsBanks,
                 bankConflictPenalty=args.ldsBankConflictPenalty,
@@ -563,7 +489,6 @@ for i in range(n_cu):
     vrfs = []
     vrf_pool_mgrs = []
     srfs = []
-    rfcs = []
     srf_pool_mgrs = []
     for j in range(args.simds_per_cu):
         for k in range(shader.n_wf):
@@ -608,16 +533,10 @@ for i in range(n_cu):
                 simd_id=j, wf_size=args.wf_size, num_regs=args.sreg_file_size
             )
         )
-        rfcs.append(
-            RegisterFileCache(
-                simd_id=j, cache_size=args.register_file_cache_size
-            )
-        )
 
     compute_units[-1].wavefronts = wavefronts
     compute_units[-1].vector_register_file = vrfs
     compute_units[-1].scalar_register_file = srfs
-    compute_units[-1].register_file_cache = rfcs
     compute_units[-1].register_manager = RegisterManager(
         policy=args.registerManagerPolicy,
         vrf_pool_managers=vrf_pool_mgrs,
@@ -648,7 +567,7 @@ cp_list = []
 cpu_list = []
 
 CpuClass, mem_mode = Simulation.getCPUClass(args.cpu_type)
-if CpuClass == X86AtomicSimpleCPU or CpuClass == AtomicSimpleCPU:
+if CpuClass == AtomicSimpleCPU:
     fatal("AtomicSimpleCPU is not supported")
 if mem_mode != "timing":
     fatal("Only the timing memory mode is supported")
@@ -748,13 +667,12 @@ render_driver = GPURenderDriver(filename=f"dri/renderD{renderDriNum}")
 gpu_hsapp = HSAPacketProcessor(
     pioAddr=hsapp_gpu_map_paddr, numHWQueues=args.num_hw_queues
 )
-dispatcher = GPUDispatcher(kernel_exit_events=True)
+dispatcher = GPUDispatcher()
 gpu_cmd_proc = GPUCommandProcessor(hsapp=gpu_hsapp, dispatcher=dispatcher)
 gpu_driver.device = gpu_cmd_proc
 shader.dispatcher = dispatcher
 shader.gpu_cmd_proc = gpu_cmd_proc
 
-
 # Create and assign the workload Check for rel_path in elements of
 # base_list using test, returning the first full path that satisfies test
 def find_path(base_list, rel_path, test):
@@ -780,7 +698,7 @@ if os.path.isdir(executable):
     executable = find_file(benchmark_path, args.cmd)
 
 if args.env:
-    with open(args.env) as f:
+    with open(args.env, "r") as f:
         env = [line.rstrip() for line in f]
 else:
     env = [
@@ -838,7 +756,7 @@ if fast_forward:
     ]
 
 # Other CPU strings cause bad addresses in ROCm. Revert back to M5 Simulator.
-for i, cpu in enumerate(cpu_list):
+for (i, cpu) in enumerate(cpu_list):
     for j in range(len(cpu)):
         cpu.isa[j].vendor_string = "M5 Simulator"
 
@@ -863,7 +781,7 @@ system.clk_domain = SrcClockDomain(
 
 if fast_forward:
     have_kvm_support = "BaseKvmCPU" in globals()
-    if have_kvm_support and get_supported_isas().contains(ISA.X86):
+    if have_kvm_support and get_runtime_isa() == ISA.X86:
         system.vm = KvmVM()
         system.m5ops_base = 0xFFFF0000
         for i in range(len(host_cpu.workload)):
@@ -875,8 +793,6 @@ if fast_forward:
 # configure the TLB hierarchy
 GPUTLBConfig.config_tlb_hierarchy(args, system, shader_idx)
 
-system.exit_on_work_items = True
-
 # create Ruby system
 system.piobus = IOXBar(
     width=32, response_latency=0, frontend_latency=0, forward_latency=0
@@ -904,15 +820,18 @@ for i in range(args.num_cpus):
     system.cpu[i].dcache_port = ruby_port.in_ports
 
     ruby_port.mem_request_port = system.piobus.cpu_side_ports
-
-    # X86 ISA is implied from cpu type check above
-    system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports
-    system.cpu[i].interrupts[0].int_requestor = system.piobus.cpu_side_ports
-    system.cpu[i].interrupts[0].int_responder = system.piobus.mem_side_ports
-    if fast_forward:
-        system.cpu[i].mmu.connectWalkerPorts(
-            ruby_port.in_ports, ruby_port.in_ports
-        )
+    if get_runtime_isa() == ISA.X86:
+        system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports
+        system.cpu[i].interrupts[
+            0
+        ].int_requestor = system.piobus.cpu_side_ports
+        system.cpu[i].interrupts[
+            0
+        ].int_responder = system.piobus.mem_side_ports
+        if fast_forward:
+            system.cpu[i].mmu.connectWalkerPorts(
+                ruby_port.in_ports, ruby_port.in_ports
+            )
 
 # attach CU ports to Ruby
 # Because of the peculiarities of the CP core, you may have 1 CPU but 2
@@ -935,9 +854,9 @@ gpu_port_idx = gpu_port_idx - args.num_cp * 2
 token_port_idx = 0
 for i in range(len(system.ruby._cpu_ports)):
     if isinstance(system.ruby._cpu_ports[i], VIPERCoalescer):
-        system.cpu[shader_idx].CUs[token_port_idx].gmTokenPort = (
-            system.ruby._cpu_ports[i].gmTokenPort
-        )
+        system.cpu[shader_idx].CUs[
+            token_port_idx
+        ].gmTokenPort = system.ruby._cpu_ports[i].gmTokenPort
         token_port_idx += 1
 
 wavefront_size = args.wf_size
@@ -1017,15 +936,19 @@ root = Root(system=system, full_system=False)
 # knows what type of GPU hardware we are simulating
 if args.dgpu:
     assert args.gfx_version in [
+        "gfx803",
         "gfx900",
     ], "Incorrect gfx version for dGPU"
-    if args.gfx_version == "gfx900":
+    if args.gfx_version == "gfx803":
+        hsaTopology.createFijiTopology(args)
+    elif args.gfx_version == "gfx900":
         hsaTopology.createVegaTopology(args)
 else:
     assert args.gfx_version in [
+        "gfx801",
         "gfx902",
     ], "Incorrect gfx version for APU"
-    hsaTopology.createRavenTopology(args)
+    hsaTopology.createCarrizoTopology(args)
 
 m5.ticks.setGlobalFrequency("1THz")
 if args.abs_max_tick:
@@ -1051,41 +974,6 @@ if args.fast_forward:
 
 exit_event = m5.simulate(maxtick)
 
-while True:
-    if (
-        exit_event.getCause() == "m5_exit instruction encountered"
-        or exit_event.getCause() == "user interrupt received"
-        or exit_event.getCause() == "simulate() limit reached"
-        or "exiting with last active thread context" in exit_event.getCause()
-    ):
-        print(f"breaking loop due to: {exit_event.getCause()}.")
-        break
-    elif "checkpoint" in exit_event.getCause():
-        assert args.checkpoint_dir is not None
-        m5.checkpoint(args.checkpoint_dir)
-        print("breaking loop with checkpoint")
-        break
-    elif "GPU Kernel Completed" in exit_event.getCause():
-        print("GPU Kernel Completed dump and reset")
-        m5.stats.dump()
-        m5.stats.reset()
-    elif "GPU Blit Kernel Completed" in exit_event.getCause():
-        print("GPU Blit Kernel Completed dump and reset")
-        m5.stats.dump()
-        m5.stats.reset()
-    elif "workbegin" in exit_event.getCause():
-        print("m5 work begin dump and reset")
-        m5.stats.dump()
-        m5.stats.reset()
-    elif "workend" in exit_event.getCause():
-        print("m5 work end dump and reset")
-        m5.stats.dump()
-        m5.stats.reset()
-    else:
-        print(f"Unknown exit event: {exit_event.getCause()}. Continuing...")
-
-    exit_event = m5.simulate(maxtick - m5.curTick())
-
 if args.fast_forward:
     if exit_event.getCause() == "a thread reached the max instruction count":
         m5.switchCpus(system, switch_cpu_list)

configs/example/arm/baremetal.py

@@ -39,29 +39,24 @@ Research Starter Kit on System Modeling. More information can be found
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """
 
-import argparse
 import os
-
 import m5
+from m5.util import addToPath
 from m5.objects import *
 from m5.options import *
-from m5.util import addToPath
-
 from gem5.simulate.exit_event import ExitEvent
+import argparse
 
 m5.util.addToPath("../..")
 
+from common import SysPaths
+from common import MemConfig
+from common import ObjectList
+from common.cores.arm import HPI
+from common.cores.arm import O3_ARM_v7a
+
 import devices
 import workloads
-from common import (
-    MemConfig,
-    ObjectList,
-    SysPaths,
-)
-from common.cores.arm import (
-    HPI,
-    O3_ARM_v7a,
-)
 
 # Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
 # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
@@ -176,10 +171,9 @@ def create(args):
     system.workload = workload_class(object_file, system)
 
     if args.with_pmu:
-        enabled_pmu_events = {
-            *args.pmu_dump_stats_on,
-            *args.pmu_reset_stats_on,
-        }
+        enabled_pmu_events = set(
+            (*args.pmu_dump_stats_on, *args.pmu_reset_stats_on)
+        )
         exit_sim_on_control = bool(
             enabled_pmu_events & set(pmu_control_events.keys())
         )
@@ -308,7 +302,7 @@ def main():
         "--mem-size",
         action="store",
         type=str,
-        default="2GiB",
+        default="2GB",
         help="Specify the physical memory size",
     )
     parser.add_argument("--checkpoint", action="store_true")

configs/example/arm/devices.py

@@ -39,8 +39,8 @@ import m5
 from m5.objects import *
 
 m5.util.addToPath("../../")
-from common import ObjectList
 from common.Caches import *
+from common import ObjectList
 
 have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
 have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()
@@ -52,7 +52,7 @@ class L1I(L1_ICache):
     response_latency = 1
     mshrs = 4
     tgts_per_mshr = 8
-    size = "48KiB"
+    size = "48kB"
     assoc = 3
 
 
@@ -62,7 +62,7 @@ class L1D(L1_DCache):
     response_latency = 1
     mshrs = 16
     tgts_per_mshr = 16
-    size = "32KiB"
+    size = "32kB"
     assoc = 2
     write_buffers = 16
 
@@ -73,14 +73,14 @@ class L2(L2Cache):
     response_latency = 5
     mshrs = 32
     tgts_per_mshr = 8
-    size = "1MiB"
+    size = "1MB"
     assoc = 16
     write_buffers = 8
     clusivity = "mostly_excl"
 
 
 class L3(Cache):
-    size = "16MiB"
+    size = "16MB"
     assoc = 16
     tag_latency = 20
     data_latency = 20
@@ -338,15 +338,56 @@ class FastmodelCluster(CpuCluster):
         pass
 
 
-class ClusterSystem:
-    """
-    Base class providing cpu clusters generation/handling methods to
-    SE/FS systems
-    """
+class BaseSimpleSystem(ArmSystem):
+    cache_line_size = 64
+
+    def __init__(self, mem_size, platform, **kwargs):
+        super(BaseSimpleSystem, self).__init__(**kwargs)
+
+        self.voltage_domain = VoltageDomain(voltage="1.0V")
+        self.clk_domain = SrcClockDomain(
+            clock="1GHz", voltage_domain=Parent.voltage_domain
+        )
+
+        if platform is None:
+            self.realview = VExpress_GEM5_V1()
+        else:
+            self.realview = platform
+
+        if hasattr(self.realview.gic, "cpu_addr"):
+            self.gic_cpu_addr = self.realview.gic.cpu_addr
+
+        self.terminal = Terminal()
+        self.vncserver = VncServer()
+
+        self.iobus = IOXBar()
+        # Device DMA -> MEM
+        self.mem_ranges = self.getMemRanges(int(Addr(mem_size)))
 
-    def __init__(self, **kwargs):
         self._clusters = []
 
+    def getMemRanges(self, mem_size):
+        """
+        Define system memory ranges. This depends on the physical
+        memory map provided by the realview platform and by the memory
+        size provided by the user (mem_size argument).
+        The method is iterating over all platform ranges until they cover
+        the entire user's memory requirements.
+        """
+        mem_ranges = []
+        for mem_range in self.realview._mem_regions:
+            size_in_range = min(mem_size, mem_range.size())
+
+            mem_ranges.append(
+                AddrRange(start=mem_range.start, size=size_in_range)
+            )
+
+            mem_size -= size_in_range
+            if mem_size == 0:
+                return mem_ranges
+
+        raise ValueError("memory size too big for platform capabilities")
+
     def numCpuClusters(self):
         return len(self._clusters)
 
@@ -382,87 +423,13 @@ class ClusterSystem:
             cluster.connectMemSide(cluster_mem_bus)
 
 
-class SimpleSeSystem(System, ClusterSystem):
-    """
-    Example system class for syscall emulation mode
-    """
-
-    # Use a fixed cache line size of 64 bytes
-    cache_line_size = 64
-
-    def __init__(self, **kwargs):
-        System.__init__(self, **kwargs)
-        ClusterSystem.__init__(self, **kwargs)
-        # Create a voltage and clock domain for system components
-        self.voltage_domain = VoltageDomain(voltage="3.3V")
-        self.clk_domain = SrcClockDomain(
-            clock="1GHz", voltage_domain=self.voltage_domain
-        )
-
-        # Create the off-chip memory bus.
-        self.membus = SystemXBar()
-
-    def connect(self):
-        self.system_port = self.membus.cpu_side_ports
-
-
-class BaseSimpleSystem(ArmSystem, ClusterSystem):
-    cache_line_size = 64
-
-    def __init__(self, mem_size, platform, **kwargs):
-        ArmSystem.__init__(self, **kwargs)
-        ClusterSystem.__init__(self, **kwargs)
-
-        self.voltage_domain = VoltageDomain(voltage="1.0V")
-        self.clk_domain = SrcClockDomain(
-            clock="1GHz", voltage_domain=Parent.voltage_domain
-        )
-
-        if platform is None:
-            self.realview = VExpress_GEM5_V1()
-        else:
-            self.realview = platform
-
-        if hasattr(self.realview.gic, "cpu_addr"):
-            self.gic_cpu_addr = self.realview.gic.cpu_addr
-
-        self.terminal = Terminal()
-        self.vncserver = VncServer()
-
-        self.iobus = IOXBar()
-        # Device DMA -> MEM
-        self.mem_ranges = self.getMemRanges(int(Addr(mem_size)))
-
-    def getMemRanges(self, mem_size):
-        """
-        Define system memory ranges. This depends on the physical
-        memory map provided by the realview platform and by the memory
-        size provided by the user (mem_size argument).
-        The method is iterating over all platform ranges until they cover
-        the entire user's memory requirements.
-        """
-        mem_ranges = []
-        for mem_range in self.realview._mem_regions:
-            size_in_range = min(mem_size, mem_range.size())
-
-            mem_ranges.append(
-                AddrRange(start=mem_range.start, size=size_in_range)
-            )
-
-            mem_size -= size_in_range
-            if mem_size == 0:
-                return mem_ranges
-
-        raise ValueError("memory size too big for platform capabilities")
-
-
 class SimpleSystem(BaseSimpleSystem):
     """
     Meant to be used with the classic memory model
     """
 
     def __init__(self, caches, mem_size, platform=None, **kwargs):
-        super().__init__(mem_size, platform, **kwargs)
+        super(SimpleSystem, self).__init__(mem_size, platform, **kwargs)
 
         self.membus = MemBus()
         # CPUs->PIO
@@ -501,7 +468,7 @@ class ArmRubySystem(BaseSimpleSystem):
     """
 
     def __init__(self, mem_size, platform=None, **kwargs):
-        super().__init__(mem_size, platform, **kwargs)
+        super(ArmRubySystem, self).__init__(mem_size, platform, **kwargs)
         self._dma_ports = []
         self._mem_ports = []
 

configs/example/arm/dist_bigLITTLE.py

@@ -39,11 +39,11 @@
 import argparse
 import os
 
-import fs_bigLITTLE as bL
-
 import m5
 from m5.objects import *
 
+import fs_bigLITTLE as bL
+
 m5.util.addToPath("../../dist")
 import sw
 

configs/example/arm/etrace_se.py

@@ -1,191 +0,0 @@
-# Copyright (c) 2016-2017, 2022-2023 Arm Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder.  You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
-import argparse
-import os
-import shlex
-
-import m5
-from m5.objects import *
-from m5.util import addToPath
-
-m5.util.addToPath("../..")
-
-import devices
-from common import ObjectList
-
-
-def get_processes(cmd):
-    """Interprets commands to run and returns a list of processes"""
-
-    cwd = os.getcwd()
-    multiprocesses = []
-    for idx, c in enumerate(cmd):
-        argv = shlex.split(c)
-
-        process = Process(pid=100 + idx, cwd=cwd, cmd=argv, executable=argv[0])
-        process.gid = os.getgid()
-
-        print("info: %d. command and arguments: %s" % (idx + 1, process.cmd))
-        multiprocesses.append(process)
-
-    return multiprocesses
-
-
-def create(args):
-    """Create and configure the system object."""
-
-    system = devices.SimpleSeSystem(
-        mem_mode="timing",
-    )
-
-    # Add CPUs to the system. A cluster of CPUs typically have
-    # private L1 caches and a shared L2 cache.
-    system.cpu_cluster = devices.ArmCpuCluster(
-        system,
-        args.num_cores,
-        args.cpu_freq,
-        "1.2V",
-        ObjectList.cpu_list.get("O3_ARM_v7a_3_Etrace"),
-        devices.L1I,
-        devices.L1D,
-        devices.L2,
-    )
-
-    # Attach the elastic trace probe listener to every CPU in the cluster
-    for cpu in system.cpu_cluster:
-        cpu.attach_probe_listener(args.inst_trace_file, args.data_trace_file)
-
-    # As elastic trace generation is enabled, make sure the memory system is
-    # minimal so that compute delays do not include memory access latencies.
-    # Configure the compulsory L1 caches for the O3CPU, do not configure
-    # any more caches.
-    system.addCaches(True, last_cache_level=1)
-
-    # For elastic trace, over-riding Simple Memory latency to 1ns."
-    system.memory = SimpleMemory(
-        range=AddrRange(start=0, size=args.mem_size),
-        latency="1ns",
-        port=system.membus.mem_side_ports,
-    )
-
-    # Parse the command line and get a list of Processes instances
-    # that we can pass to gem5.
-    processes = get_processes(args.commands_to_run)
-    if len(processes) != args.num_cores:
-        print(
-            "Error: Cannot map %d command(s) onto %d CPU(s)"
-            % (len(processes), args.num_cores)
-        )
-        sys.exit(1)
-
-    system.workload = SEWorkload.init_compatible(processes[0].executable)
-
-    # Assign one workload to each CPU
-    for cpu, workload in zip(system.cpu_cluster.cpus, processes):
-        cpu.workload = workload
-
-    return system
-
-
-def main():
-    parser = argparse.ArgumentParser(epilog=__doc__)
-
-    parser.add_argument(
-        "commands_to_run",
-        metavar="command(s)",
-        nargs="+",
-        help="Command(s) to run",
-    )
-    parser.add_argument(
-        "--inst-trace-file",
-        action="store",
-        type=str,
-        help="""Instruction fetch trace file input to
-                Elastic Trace probe in a capture simulation and
-                Trace CPU in a replay simulation""",
-        default="fetchtrace.proto.gz",
-    )
-    parser.add_argument(
-        "--data-trace-file",
-        action="store",
-        type=str,
-        help="""Data dependency trace file input to
-                Elastic Trace probe in a capture simulation and
-                Trace CPU in a replay simulation""",
-        default="deptrace.proto.gz",
-    )
-    parser.add_argument("--cpu-freq", type=str, default="4GHz")
-    parser.add_argument(
-        "--num-cores", type=int, default=1, help="Number of CPU cores"
-    )
-    parser.add_argument(
-        "--mem-size",
-        action="store",
-        type=str,
-        default="2GiB",
-        help="Specify the physical memory size",
-    )
-
-    args = parser.parse_args()
-
-    # Create a single root node for gem5's object hierarchy. There can
-    # only exist one root node in the simulator at any given
-    # time. Tell gem5 that we want to use syscall emulation mode
-    # instead of full system mode.
-    root = Root(full_system=False)
-
-    # Populate the root node with a system. A system corresponds to a
-    # single node with shared memory.
-    root.system = create(args)
-
-    # Instantiate the C++ object hierarchy. After this point,
-    # SimObjects can't be instantiated anymore.
-    m5.instantiate()
-
-    # Start the simulator. This gives control to the C++ world and
-    # starts the simulator. The returned event tells the simulation
-    # script why the simulator exited.
-    event = m5.simulate()
-
-    # Print the reason for the simulation exit. Some exit codes are
-    # requests for service (e.g., checkpoints) from the simulation
-    # script. We'll just ignore them here and exit.
-    print(f"{event.getCause()} ({event.getCode()}) @ {m5.curTick()}")
-
-
-if __name__ == "__m5_main__":
-    main()

configs/example/arm/fs_bigLITTLE.py

@@ -39,33 +39,25 @@
 import argparse
 import os
 import sys
-
 import m5
 import m5.util
 from m5.objects import *
 
 m5.util.addToPath("../../")
 
+from common import FSConfig
+from common import SysPaths
+from common import ObjectList
+from common import Options
+from common.cores.arm import ex5_big, ex5_LITTLE
+
 import devices
-from common import (
-    FSConfig,
-    ObjectList,
-    Options,
-    SysPaths,
-)
-from common.cores.arm import (
-    ex5_big,
-    ex5_LITTLE,
-)
-from devices import (
-    AtomicCluster,
-    FastmodelCluster,
-    KvmCluster,
-)
+from devices import AtomicCluster, KvmCluster, FastmodelCluster
+
 
 default_disk = "aarch64-ubuntu-trusty-headless.img"
 
-default_mem_size = "2GiB"
+default_mem_size = "2GB"
 
 
 def _to_ticks(value):
@@ -418,8 +410,7 @@ def build(options):
         system.generateDtb(system.workload.dtb_filename)
 
     if devices.have_fastmodel and issubclass(big_model, FastmodelCluster):
-        from m5 import arm_fast_model as fm
-        from m5 import systemc as sc
+        from m5 import arm_fast_model as fm, systemc as sc
 
         # setup FastModels for simulation
         fm.setup_simulation("cortexa76")

configs/example/arm/fs_power.py

@@ -39,18 +39,15 @@
 import argparse
 import os
 
-import fs_bigLITTLE as bL
-
 import m5
-from m5.objects import (
-    MathExprPowerModel,
-    PowerModel,
-)
+from m5.objects import MathExprPowerModel, PowerModel
+
+import fs_bigLITTLE as bL
 
 
 class CpuPowerOn(MathExprPowerModel):
     def __init__(self, cpu_path, **kwargs):
-        super().__init__(**kwargs)
+        super(CpuPowerOn, self).__init__(**kwargs)
         # 2A per IPC, 3pA per cache miss
         # and then convert to Watt
         self.dyn = (
@@ -67,7 +64,7 @@ class CpuPowerOff(MathExprPowerModel):
 
 class CpuPowerModel(PowerModel):
     def __init__(self, cpu_path, **kwargs):
-        super().__init__(**kwargs)
+        super(CpuPowerModel, self).__init__(**kwargs)
         self.pm = [
             CpuPowerOn(cpu_path),  # ON
             CpuPowerOff(),  # CLK_GATED
@@ -78,7 +75,7 @@ class CpuPowerModel(PowerModel):
 
 class L2PowerOn(MathExprPowerModel):
     def __init__(self, l2_path, **kwargs):
-        super().__init__(**kwargs)
+        super(L2PowerOn, self).__init__(**kwargs)
         # Example to report l2 Cache overallAccesses
         # The estimated power is converted to Watt and will vary based
         # on the size of the cache
@@ -93,7 +90,7 @@ class L2PowerOff(MathExprPowerModel):
 
 class L2PowerModel(PowerModel):
     def __init__(self, l2_path, **kwargs):
-        super().__init__(**kwargs)
+        super(L2PowerModel, self).__init__(**kwargs)
         # Choose a power model for every power state
         self.pm = [
             L2PowerOn(l2_path),  # ON

configs/example/arm/ruby_fs.py

@@ -33,29 +33,25 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import argparse
 import os
-
 import m5
+from m5.util import addToPath
 from m5.objects import *
 from m5.options import *
-from m5.util import addToPath
+import argparse
 
 m5.util.addToPath("../..")
 
-import devices
-from common import (
-    MemConfig,
-    ObjectList,
-    Options,
-    SysPaths,
-)
-from common.cores.arm import (
-    HPI,
-    O3_ARM_v7a,
-)
+from common import MemConfig
+from common import ObjectList
+from common import Options
+from common import SysPaths
+from common.cores.arm import O3_ARM_v7a, HPI
 from ruby import Ruby
 
+import devices
+
+
 default_kernel = "vmlinux.arm64"
 default_disk = "linaro-minimal-aarch64.img"
 default_root_device = "/dev/vda1"
@@ -278,10 +274,10 @@ def main():
     parser.add_argument("--num-dirs", type=int, default=1)
     parser.add_argument("--num-l2caches", type=int, default=1)
     parser.add_argument("--num-l3caches", type=int, default=1)
-    parser.add_argument("--l1d_size", type=str, default="64KiB")
-    parser.add_argument("--l1i_size", type=str, default="32KiB")
-    parser.add_argument("--l2_size", type=str, default="2MiB")
-    parser.add_argument("--l3_size", type=str, default="16MiB")
+    parser.add_argument("--l1d_size", type=str, default="64kB")
+    parser.add_argument("--l1i_size", type=str, default="32kB")
+    parser.add_argument("--l2_size", type=str, default="2MB")
+    parser.add_argument("--l3_size", type=str, default="16MB")
     parser.add_argument("--l1d_assoc", type=int, default=2)
     parser.add_argument("--l1i_assoc", type=int, default=2)
     parser.add_argument("--l2_assoc", type=int, default=8)

configs/example/arm/starter_fs.py

@@ -38,26 +38,22 @@ Research Starter Kit on System Modeling. More information can be found
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """
 
-import argparse
 import os
-
 import m5
+from m5.util import addToPath
 from m5.objects import *
 from m5.options import *
-from m5.util import addToPath
+import argparse
 
 m5.util.addToPath("../..")
 
+from common import SysPaths
+from common import ObjectList
+from common import MemConfig
+from common.cores.arm import O3_ARM_v7a, HPI
+
 import devices
-from common import (
-    MemConfig,
-    ObjectList,
-    SysPaths,
-)
-from common.cores.arm import (
-    HPI,
-    O3_ARM_v7a,
-)
+
 
 default_kernel = "vmlinux.arm64"
 default_disk = "linaro-minimal-aarch64.img"
@@ -276,7 +272,7 @@ def main():
         "--mem-size",
         action="store",
         type=str,
-        default="2GiB",
+        default="2GB",
         help="Specify the physical memory size",
     )
     parser.add_argument(

configs/example/arm/starter_se.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2022-2024 Arm Limited
+# Copyright (c) 2016-2017, 2022-2023 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -38,42 +38,98 @@ Research Starter Kit on System Modeling. More information can be found
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """
 
-import argparse
 import os
-import shlex
-
 import m5
-from m5.objects import *
 from m5.util import addToPath
+from m5.objects import *
+import argparse
+import shlex
 
 m5.util.addToPath("../..")
 
+from common import ObjectList
+from common import MemConfig
+from common.cores.arm import HPI
+
 import devices
-from common import (
-    MemConfig,
-    ObjectList,
-)
-from common.cores.arm import (
-    HPI,
-    O3_ARM_v7a,
-)
+
 
 # Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
-# l1_icache_class, l1_dcache_class, l2_Cache_class). Any of
+# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
 # the cache class may be 'None' if the particular cache is not present.
 cpu_types = {
     "atomic": (AtomicSimpleCPU, None, None, None),
     "minor": (MinorCPU, devices.L1I, devices.L1D, devices.L2),
     "hpi": (HPI.HPI, HPI.HPI_ICache, HPI.HPI_DCache, HPI.HPI_L2),
-    "o3": (
-        O3_ARM_v7a.O3_ARM_v7a_3,
-        O3_ARM_v7a.O3_ARM_v7a_ICache,
-        O3_ARM_v7a.O3_ARM_v7a_DCache,
-        O3_ARM_v7a.O3_ARM_v7aL2,
-    ),
 }
 
 
+class SimpleSeSystem(System):
+    """
+    Example system class for syscall emulation mode
+    """
+
+    # Use a fixed cache line size of 64 bytes
+    cache_line_size = 64
+
+    def __init__(self, args, **kwargs):
+        super(SimpleSeSystem, self).__init__(**kwargs)
+
+        # Setup book keeping to be able to use CpuClusters from the
+        # devices module.
+        self._clusters = []
+        self._num_cpus = 0
+
+        # Create a voltage and clock domain for system components
+        self.voltage_domain = VoltageDomain(voltage="3.3V")
+        self.clk_domain = SrcClockDomain(
+            clock="1GHz", voltage_domain=self.voltage_domain
+        )
+
+        # Create the off-chip memory bus.
+        self.membus = SystemXBar()
+
+        # Wire up the system port that gem5 uses to load the kernel
+        # and to perform debug accesses.
+        self.system_port = self.membus.cpu_side_ports
+
+        # Add CPUs to the system. A cluster of CPUs typically have
+        # private L1 caches and a shared L2 cache.
+        self.cpu_cluster = devices.ArmCpuCluster(
+            self,
+            args.num_cores,
+            args.cpu_freq,
+            "1.2V",
+            *cpu_types[args.cpu],
+            tarmac_gen=args.tarmac_gen,
+            tarmac_dest=args.tarmac_dest,
+        )
+
+        # Create a cache hierarchy (unless we are simulating a
+        # functional CPU in atomic memory mode) for the CPU cluster
+        # and connect it to the shared memory bus.
+        if self.cpu_cluster.memory_mode() == "timing":
+            self.cpu_cluster.addL1()
+            self.cpu_cluster.addL2(self.cpu_cluster.clk_domain)
+        self.cpu_cluster.connectMemSide(self.membus)
+
+        # Tell gem5 about the memory mode used by the CPUs we are
+        # simulating.
+        self.mem_mode = self.cpu_cluster.memory_mode()
+
+    def numCpuClusters(self):
+        return len(self._clusters)
+
+    def addCpuCluster(self, cpu_cluster):
+        assert cpu_cluster not in self._clusters
+        assert len(cpu_cluster) > 0
+        self._clusters.append(cpu_cluster)
+        self._num_cpus += len(cpu_cluster)
+
+    def numCpus(self):
+        return self._num_cpus
+
+
 def get_processes(cmd):
     """Interprets commands to run and returns a list of processes"""
 
@@ -94,31 +150,7 @@ def get_processes(cmd):
 def create(args):
     """Create and configure the system object."""
 
-    cpu_class = cpu_types[args.cpu][0]
-    mem_mode = cpu_class.memory_mode()
-    # Only simulate caches when using a timing CPU (e.g., the HPI model)
-    want_caches = True if mem_mode == "timing" else False
-
-    system = devices.SimpleSeSystem(
-        mem_mode=mem_mode,
-    )
-
-    # Add CPUs to the system. A cluster of CPUs typically have
-    # private L1 caches and a shared L2 cache.
-    system.cpu_cluster = devices.ArmCpuCluster(
-        system,
-        args.num_cores,
-        args.cpu_freq,
-        "1.2V",
-        *cpu_types[args.cpu],
-        tarmac_gen=args.tarmac_gen,
-        tarmac_dest=args.tarmac_dest,
-    )
-
-    # Create a cache hierarchy for the cluster. We are assuming that
-    # clusters have core-private L1 caches and an L2 that's shared
-    # within the cluster.
-    system.addCaches(want_caches, last_cache_level=2)
+    system = SimpleSeSystem(args)
 
     # Tell components about the expected physical memory ranges. This
     # is, for example, used by the MemConfig helper to determine where
@@ -128,9 +160,6 @@ def create(args):
     # Configure the off-chip memory system.
     MemConfig.config_mem(args, system)
 
-    # Wire up the system's memory system
-    system.connect()
-
     # Parse the command line and get a list of Processes instances
     # that we can pass to gem5.
     processes = get_processes(args.commands_to_run)
@@ -189,7 +218,7 @@ def main():
         "--mem-size",
         action="store",
         type=str,
-        default="2GiB",
+        default="2GB",
         help="Specify the physical memory size",
     )
     parser.add_argument(
@@ -203,19 +232,6 @@ def main():
         default="stdoutput",
         help="Destination for the Tarmac trace output. [Default: stdoutput]",
     )
-    parser.add_argument(
-        "-P",
-        "--param",
-        action="append",
-        default=[],
-        help="Set a SimObject parameter relative to the root node. "
-        "An extended Python multi range slicing syntax can be used "
-        "for arrays. For example: "
-        "'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' "
-        "sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 "
-        "Direct parameters of the root object are not accessible, "
-        "only parameters of its children.",
-    )
 
     args = parser.parse_args()
 
@@ -228,7 +244,6 @@ def main():
     # Populate the root node with a system. A system corresponds to a
     # single node with shared memory.
     root.system = create(args)
-    root.apply_config(args.param)
 
     # Instantiate the C++ object hierarchy. After this point,
     # SimObjects can't be instantiated anymore.

configs/example/arm/workloads.py

@@ -35,17 +35,13 @@
 #
 
 import inspect
-
-from common.ObjectList import ObjectList
-from common.SysPaths import (
-    binary,
-    disk,
-)
-
 import m5
 from m5.objects import *
 from m5.options import *
 
+from common.ObjectList import ObjectList
+from common.SysPaths import binary, disk
+
 
 class ArmBaremetal(ArmFsWorkload):
     """Baremetal workload"""
@@ -53,7 +49,7 @@ class ArmBaremetal(ArmFsWorkload):
     dtb_addr = 0
 
     def __init__(self, obj, system, **kwargs):
-        super().__init__(**kwargs)
+        super(ArmBaremetal, self).__init__(**kwargs)
 
         self.object_file = obj
 
@@ -80,7 +76,7 @@ class ArmTrustedFirmware(ArmFsWorkload):
     dtb_addr = 0
 
     def __init__(self, obj, system, **kwargs):
-        super().__init__(**kwargs)
+        super(ArmTrustedFirmware, self).__init__(**kwargs)
 
         self.extras = [binary("bl1.bin"), binary("fip.bin")]
         self.extras_addrs = [

configs/example/cache_partitioning.py

@@ -1,201 +0,0 @@
-# Copyright (c) 2024 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder.  You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-# This script showcases the functionality of cache partitioning policies,
-# containg a simple system comprised of a memory requestor (TrafficGen),
-# a cache enforcing policies for requests and a SimpleMemory backing store.
-#
-# Using the Way policy, the cache should show the following statistics in the
-# provided configuration:
-#
-# | Allocated Ways | 1 | 2   | 3   | 4   | 5   | 6   | 7   | 8    |
-# |----------------|---|-----|-----|-----|-----|-----|-----|------|
-# | Cache Hits     | 0 | 256 | 384 | 512 | 640 | 768 | 896 | 1024 |
-#
-# Using the MaxCapacity policy, expected results are the following:
-#
-# | Allocation % | 10 | 20  | 30  | 40  | 50  | 60  | 70  | 80  | 90  | 100  |
-# |--------------|----|-----|-----|-----|-----|-----|-----|-----|-----|------|
-# | Cache Hits   | 0  | 152 | 307 | 409 | 512 | 614 | 716 | 819 | 921 | 1024 |
-
-import argparse
-
-import m5
-from m5.objects import *
-
-
-def capacityAllocation(capacity_str):
-    """
-    Verify that Max Capacity partitioning policy has been provided with a suitable
-    configuration
-    """
-    capacity = float(capacity_str)
-
-    if capacity > 1 or capacity < 0:
-        raise argparse.ArgumentTypeError(
-            "Max Capacity Policy needs allocation in range [0, 1]"
-        )
-
-    return capacity
-
-
-def wayAllocation(way_str):
-    """
-    Verify that Way partitioning policy has been provided with a suitable
-    configuration
-    """
-    way_alloc = int(way_str)
-
-    if way_alloc < 0:
-        raise argparse.ArgumentTypeError(
-            "Way Policy needs positive number of ways"
-        )
-
-    return way_alloc
-
-
-def generatePartPolicy(args):
-    """
-    Generate Partitioning Policy object based on provided arguments
-    """
-    assert args.policy in [
-        "way",
-        "max_capacity",
-    ], "Only support generating way and max_capacity policies"
-
-    if args.policy == "way":
-        allocated_ways = [way for way in range(0, args.way_allocation)]
-        allocation = WayPolicyAllocation(partition_id=0, ways=allocated_ways)
-
-        return WayPartitioningPolicy(allocations=[allocation])
-
-    if args.policy == "max_capacity":
-        return MaxCapacityPartitioningPolicy(
-            partition_ids=[0], capacities=[args.capacity_allocation]
-        )
-
-
-def configSystem():
-    """
-    Configure base system and memory
-    """
-
-    system = System(membus=IOXBar(width=128))
-    system.clk_domain = SrcClockDomain(
-        clock="10THz",
-        voltage_domain=VoltageDomain(),
-    )
-
-    # Memory configuration
-    system.mem_ctrl = SimpleMemory(bandwidth="1GiB/s", latency="10ns")
-
-    # add memory
-    system.mem_ctrl.range = AddrRange("64KiB")
-    system.mem_ctrl.port = system.membus.mem_side_ports
-    return system
-
-
-parser = argparse.ArgumentParser(
-    formatter_class=argparse.ArgumentDefaultsHelpFormatter
-)
-
-parser.add_argument(
-    "--policy",
-    default="way",
-    choices=["way", "max_capacity"],
-    help="This option defines which Cache Partitioning Policy to use for "
-    "the system cache",
-)
-
-parser.add_argument(
-    "--capacity-allocation",
-    type=capacityAllocation,
-    default=0.5,
-    help="The amount of the cache to partition to the default PartitionID "
-    "when using Max Capacity Cache Partitioning Policy in [0,1] range",
-)
-
-parser.add_argument(
-    "--way-allocation",
-    type=wayAllocation,
-    default=4,
-    help="The number of ways in the cache to partition to the default "
-    "PartitionID when using Way Cache Partitioning Policy",
-)
-
-args = parser.parse_args()
-
-m5.ticks.setGlobalFrequency("10THz")
-system = configSystem()
-
-# create a cache to sit between the memory and traffic gen to enforce
-# partitioning policies
-part_manager = PartitionManager(
-    partitioning_policies=[generatePartPolicy(args)]
-)
-system.cache = NoncoherentCache(
-    size="64KiB",
-    assoc=8,
-    partitioning_manager=part_manager,
-    tag_latency=0,
-    data_latency=0,
-    response_latency=0,
-    mshrs=1,
-    tgts_per_mshr=8,
-    write_buffers=1,
-    replacement_policy=MRURP(),
-)
-system.cache.mem_side = system.membus.cpu_side_ports
-
-# instantiate traffic gen and connect to crossbar
-system.tgen = PyTrafficGen()
-system.tgen.port = system.cache.cpu_side
-
-# finalise config and run simulation
-root = Root(full_system=False, system=system)
-root.system.mem_mode = "timing"
-m5.instantiate()
-
-# configure traffic generator to do 2x 64KiB sequential reads from address 0
-# to 65536; one to warm up the cache one to test cache partitioning
-linear_tgen = system.tgen.createLinear(
-    1000000000, 0, 65536, 64, 1, 1, 100, 65536
-)
-exit_tgen = system.tgen.createExit(1)
-system.tgen.start([linear_tgen, linear_tgen, exit_tgen])
-
-# handle exit reporting
-exit_event = m5.simulate(2000000000)
-print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")

configs/example/dramsys.py

@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import m5
+
 from m5.objects import *
 
 traffic_gen = PyTrafficGen()

configs/example/etrace_replay.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2015, 2023 Arm Limited
+# Copyright (c) 2015 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -37,53 +37,16 @@
 
 import argparse
 
-from m5.util import (
-    addToPath,
-    fatal,
-)
+from m5.util import addToPath, fatal
 
 addToPath("../")
 
-from common import (
-    MemConfig,
-    Options,
-    Simulation,
-)
+from common import Options
+from common import Simulation
+from common import CacheConfig
+from common import MemConfig
 from common.Caches import *
 
-
-def config_cache(args, system):
-    """
-    Configure the cache hierarchy.  Only two configurations are natively
-    supported as an example: L1(I/D) only or L1 + L2.
-    """
-    from common.CacheConfig import _get_cache_opts
-
-    system.l1i = L1_ICache(**_get_cache_opts("l1i", args))
-    system.l1d = L1_DCache(**_get_cache_opts("l1d", args))
-
-    system.cpu.dcache_port = system.l1d.cpu_side
-    system.cpu.icache_port = system.l1i.cpu_side
-
-    if args.l2cache:
-        # Provide a clock for the L2 and the L1-to-L2 bus here as they
-        # are not connected using addTwoLevelCacheHierarchy. Use the
-        # same clock as the CPUs.
-        system.l2 = L2Cache(
-            clk_domain=system.cpu_clk_domain, **_get_cache_opts("l2", args)
-        )
-
-        system.tol2bus = L2XBar(clk_domain=system.cpu_clk_domain)
-        system.l2.cpu_side = system.tol2bus.mem_side_ports
-        system.l2.mem_side = system.membus.cpu_side_ports
-
-        system.l1i.mem_side = system.tol2bus.cpu_side_ports
-        system.l1d.mem_side = system.tol2bus.cpu_side_ports
-    else:
-        system.l1i.mem_side = system.membus.cpu_side_ports
-        system.l1d.mem_side = system.membus.cpu_side_ports
-
-
 parser = argparse.ArgumentParser()
 Options.addCommonOptions(parser)
 
@@ -96,18 +59,29 @@ if "--ruby" in sys.argv:
 
 args = parser.parse_args()
 
+numThreads = 1
+
+if args.cpu_type != "TraceCPU":
+    fatal(
+        "This is a script for elastic trace replay simulation, use "
+        "--cpu-type=TraceCPU\n"
+    )
+
 if args.num_cpus > 1:
     fatal("This script does not support multi-processor trace replay.\n")
 
+# In this case FutureClass will be None as there is not fast forwarding or
+# switching
+(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(args)
+CPUClass.numThreads = numThreads
+
 system = System(
-    mem_mode=TraceCPU.memory_mode(),
+    cpu=CPUClass(cpu_id=0),
+    mem_mode=test_mem_mode,
     mem_ranges=[AddrRange(args.mem_size)],
     cache_line_size=args.cacheline_size,
 )
 
-# Generate the TraceCPU
-system.cpu = TraceCPU()
-
 # Create a top-level voltage domain
 system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
 
@@ -131,6 +105,11 @@ system.cpu_clk_domain = SrcClockDomain(
 for cpu in system.cpu:
     cpu.clk_domain = system.cpu_clk_domain
 
+# BaseCPU no longer has default values for the BaseCPU.isa
+# createThreads() is needed to fill in the cpu.isa
+for cpu in system.cpu:
+    cpu.createThreads()
+
 # Assign input trace files to the Trace CPU
 system.cpu.instTraceFile = args.inst_trace_file
 system.cpu.dataTraceFile = args.data_trace_file
@@ -139,11 +118,8 @@ system.cpu.dataTraceFile = args.data_trace_file
 MemClass = Simulation.setMemClass(args)
 system.membus = SystemXBar()
 system.system_port = system.membus.cpu_side_ports
-
-# Configure the classic cache hierarchy
-config_cache(args, system)
-
+CacheConfig.config_cache(args, system)
 MemConfig.config_mem(args, system)
 
 root = Root(full_system=False, system=system)
-Simulation.run(args, root, system, None)
+Simulation.run(args, root, system, FutureClass)

configs/example/garnet_synth_traffic.py

@@ -26,14 +26,11 @@
 #
 # Author: Tushar Krishna
 
-import argparse
-import os
-import sys
-
 import m5
-from m5.defines import buildEnv
 from m5.objects import *
+from m5.defines import buildEnv
 from m5.util import addToPath
+import os, argparse, sys
 
 addToPath("../")
 

configs/example/gem5_library/arm-baremetal.py

@@ -1,8 +1,3 @@
-import m5
-import json
-import dataclasses
-import sys
-
 from gem5.isas import ISA
 from m5.objects import (
     ArmDefaultRelease,
@@ -13,13 +8,9 @@ from gem5.resources.resource import BinaryResource
 from gem5.simulate.simulator import Simulator
 from m5.objects import VExpress_GEM5_Foundation
 from gem5.components.boards.arm_baremetal_board import ArmBareMetalBoard
-from gem5.components.memory import DRAMSysHBM2
+from gem5.components.memory import DRAMSysDDR3_1600
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.simulate.exit_event import ExitEvent
-from dataclasses import dataclass
-
-from pim_config import Configuration, Statistics
 
 requires(isa_required=ISA.ARM)
 
@@ -28,19 +19,18 @@ from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierar
 )
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
 
-configuration = Configuration(**json.loads(sys.argv[1]))
-
 cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
     l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
 )
+# cache_hierarchy = NoCache()
 
-memory = DRAMSysHBM2(recordable=False)
+memory = DRAMSysDDR3_1600(recordable=True)
 processor = SimpleProcessor(cpu_type=CPUTypes.O3, num_cores=1, isa=ISA.ARM)
 release = ArmDefaultRelease()
 platform = VExpress_GEM5_Foundation()
 
 board = ArmBareMetalBoard(
-    clk_freq=configuration.frequency,
+    clk_freq="3GHz",
     processor=processor,
     memory=memory,
     cache_hierarchy=cache_hierarchy,
@@ -48,52 +38,15 @@ board = ArmBareMetalBoard(
     platform=platform,
 )
 
-# HBM2 requires line size of 32 Bytes
-board.cache_line_size = 32
-
-for core in processor.get_cores():
-    core.core.fetchBufferSize = 32
+board.m5ops_base = 0x10010000
 
 workload = CustomWorkload(
     "set_baremetal_workload",
     {
-        "kernel": BinaryResource(configuration.executable),
+        "kernel": BinaryResource("aarch64"),
     },
 )
 board.set_workload(workload)
 
-
-@dataclass
-class WorkloadTime:
-    start: int
-    end: int
-
-
-workload_time = WorkloadTime(0, 0)
-
-
-def exit_event():
-    print(f"Workload begin @{m5.curTick()}")
-    workload_time.start = m5.curTick()
-    m5.stats.reset()
-    yield False
-
-    print(f"Workload end @{m5.curTick()}")
-    workload_time.end = m5.curTick()
-    m5.stats.dump()
-    yield False
-
-    print(f"Exit simulation @{m5.curTick()}...")
-    yield True
-
-
-simulator = Simulator(
-    board=board, on_exit_event={ExitEvent.EXIT: exit_event()}
-)
-
+simulator = Simulator(board=board)
 simulator.run()
-
-print(f"Workload took {workload_time.end - workload_time.start}")
-
-statistics = Statistics(workload_time.end - workload_time.start)
-print(json.dumps(dataclasses.asdict(statistics)))

configs/example/gem5_library/arm-demo-ubuntu-run.py

@@ -1,92 +0,0 @@
-# Copyright (c) 2024 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-"""
-This script further shows an example of booting an ARM based full system Ubuntu
-disk image. This simulation boots the disk image using the ArmDemoBoard.
-
-Usage
------
-
-```bash
-scons build/ARM/gem5.opt -j $(nproc)
-./build/ARM/gem5.opt configs/example/gem5_library/arm-demo-ubuntu-run.py
-```
-"""
-import argparse
-
-from gem5.isas import ISA
-from gem5.prebuilt.demo.arm_demo_board import ArmDemoBoard
-from gem5.resources.resource import obtain_resource
-from gem5.simulate.exit_event import ExitEvent
-from gem5.simulate.simulator import Simulator
-from gem5.utils.requires import requires
-
-# This runs a check to ensure the gem5 binary interpreting this file is compiled to include the ARM ISA.
-requires(isa_required=ISA.ARM)
-
-parser = argparse.ArgumentParser(
-    description="An example configuration script to run the ArmDemoBoard."
-)
-
-parser.add_argument(
-    "--use-kvm",
-    action="store_true",
-    help="Use KVM cores instead of Timing.",
-)
-args = parser.parse_args()
-
-board = ArmDemoBoard(use_kvm=args.use_kvm)
-
-board.set_workload(
-    obtain_resource(
-        "arm-ubuntu-24.04-boot-with-systemd", resource_version="2.0.0"
-    )
-)
-
-
-def exit_event_handler():
-    print("First exit: kernel booted")
-    yield False  # gem5 is now executing systemd startup
-    print("Second exit: Started `after_boot.sh` script")
-    # The after_boot.sh script is executed after the kernel and systemd have
-    # booted.
-    yield False  # gem5 is now executing the `after_boot.sh` script
-    print("Third exit: Finished `after_boot.sh` script")
-    # The after_boot.sh script will run a script if it is passed via
-    # m5 readfile. This is the last exit event before the simulation exits.
-    yield True
-
-
-# We define the system with the aforementioned system defined.
-simulator = Simulator(
-    board=board,
-    on_exit_event={
-        ExitEvent.EXIT: exit_event_handler(),
-    },
-)
-
-simulator.run()

configs/example/gem5_library/arm-hello.py

@@ -43,18 +43,13 @@ scons build/ARM/gem5.opt
 
 from gem5.isas import ISA
 from gem5.utils.requires import requires
-from gem5.resources.resource import BinaryResource
+from gem5.resources.resource import Resource
 from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
-from gem5.components.memory import SingleChannelDDR3_1600
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.isas import ISA
-from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
-from gem5.utils.requires import requires
 
 # This check ensures the gem5 binary is compiled to the ARM ISA target. If not,
 # an exception will be thrown.
@@ -64,12 +59,12 @@ requires(isa_required=ISA.ARM)
 cache_hierarchy = NoCache()
 
 # We use a single channel DDR3_1600 memory system
-memory = SingleChannelDDR3_1600(size="32MiB")
+memory = SingleChannelDDR3_1600(size="32MB")
 
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM, num_cores=1)
 
-# The gem5 library simple board which can be used to run simple SE-mode
+# The gem5 library simble board which can be used to run simple SE-mode
 # simulations.
 board = SimpleBoard(
     clk_freq="3GHz",
@@ -89,7 +84,7 @@ board.set_se_binary_workload(
     # Any resource specified in this file will be automatically retrieved.
     # At the time of writing, this file is a WIP and does not contain all
     # resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096
-    BinaryResource("physical")
+    Resource("arm-hello64-static")
 )
 
 # Lastly we run the simulation.

configs/example/gem5_library/arm-ubuntu-run-with-kvm.py

@@ -1,140 +0,0 @@
-# Copyright (c) 2022-23 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-"""
-This script further shows an example of booting an ARM based full system Ubuntu
-disk image. This simulation boots the disk image using 2 TIMING CPU cores. The
-simulation ends when the startup is completed successfully (i.e. when an
-`m5_exit instruction is reached on successful boot).
-
-Usage
------
-
-```
-scons build/ARM/gem5.opt -j<NUM_CPUS>
-./build/ARM/gem5.opt configs/example/gem5_library/arm-ubuntu-run-with-kvm.py
-```
-
-"""
-
-from m5.objects import (
-    ArmDefaultRelease,
-    VExpress_GEM5_V1,
-)
-
-from gem5.coherence_protocol import CoherenceProtocol
-from gem5.components.boards.arm_board import ArmBoard
-from gem5.components.memory import DualChannelDDR4_2400
-from gem5.components.processors.cpu_types import CPUTypes
-from gem5.components.processors.simple_switchable_processor import (
-    SimpleSwitchableProcessor,
-)
-from gem5.isas import ISA
-from gem5.resources.resource import obtain_resource
-from gem5.simulate.exit_event import ExitEvent
-from gem5.simulate.simulator import Simulator
-from gem5.utils.requires import requires
-
-# This runs a check to ensure the gem5 binary is compiled for ARM.
-requires(isa_required=ISA.ARM)
-
-from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
-    PrivateL1PrivateL2CacheHierarchy,
-)
-
-# Here we setup the parameters of the l1 and l2 caches.
-cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
-    l1d_size="16KiB", l1i_size="16KiB", l2_size="256KiB"
-)
-
-# Memory: Dual Channel DDR4 2400 DRAM device.
-memory = DualChannelDDR4_2400(size="2GiB")
-
-# Here we setup the processor. This is a special switchable processor in which
-# a starting core type and a switch core type must be specified. Once a
-# configuration is instantiated a user may call `processor.switch()` to switch
-# from the starting core types to the switch core types. In this simulation
-# we start with KVM cores to simulate the OS boot, then switch to the Timing
-# cores for the command we wish to run after boot.
-processor = SimpleSwitchableProcessor(
-    starting_core_type=CPUTypes.KVM,
-    switch_core_type=CPUTypes.TIMING,
-    isa=ISA.ARM,
-    num_cores=2,
-)
-
-# The ArmBoard requires a `release` to be specified. This adds all the
-# extensions or features to the system. We are setting this to for_kvm()
-# to enable KVM simulation.
-release = ArmDefaultRelease.for_kvm()
-
-# The platform sets up the memory ranges of all the on-chip and off-chip
-# devices present on the ARM system. ARM KVM only works with VExpress_GEM5_V1
-# on the ArmBoard at the moment.
-platform = VExpress_GEM5_V1()
-
-# Here we setup the board. The ArmBoard allows for Full-System ARM simulations.
-board = ArmBoard(
-    clk_freq="3GHz",
-    processor=processor,
-    memory=memory,
-    cache_hierarchy=cache_hierarchy,
-    release=release,
-    platform=platform,
-)
-
-# Here we set a full system workload. The "arm-ubuntu-24.04-boot-with-systemd" boots
-# Ubuntu 24.04.
-workload = obtain_resource("arm-ubuntu-24.04-boot-with-systemd")
-board.set_workload(workload)
-
-
-def exit_event_handler():
-    print("First exit: kernel booted")
-    yield False  # gem5 is now executing systemd startup
-    print("Second exit: Started `after_boot.sh` script")
-    # The after_boot.sh script is executed after the kernel and systemd have
-    # booted.
-    # Here we switch the CPU type to Timing.
-    print("Switching to Timing CPU")
-    processor.switch()
-    yield False  # gem5 is now executing the `after_boot.sh` script
-    print("Third exit: Finished `after_boot.sh` script")
-    # The after_boot.sh script will run a script if it is passed via
-    # m5 readfile. This is the last exit event before the simulation exits.
-    yield True
-
-
-simulator = Simulator(
-    board=board,
-    on_exit_event={
-        # Here we want override the default behavior for the first m5 exit
-        # exit event.
-        ExitEvent.EXIT: exit_event_handler()
-    },
-)
-
-simulator.run()