Commit Graph

18429 Commits

Author SHA1 Message Date
Gabe Black
e35812f256 ext: In sst, set sys.argv up even when not initializing python.
pybind11 gives us a simple way to set up sys.argv when initializing the
python interpreter, but we need to set that up even if the python
interpreter is already running. We need to do that manually, which we do
like gem5's main() used to.

Change-Id: If9b79a80e05158226d13f68bf06a2a98a36c2602
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54310
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-17 06:58:46 +00:00
Gabe Black
2e4b7d9091 sim,python: Use scoped_interpreter_guard's argc and argv ctor arguments.
When pybind11's scoped_interpreter_guard is constructed, it can take
argc and argv parameters which it uses to intitialize the sys.argv list
in python. We can use that mechanism instead of setting that up manually
ourselves.

Change-Id: If34fac610d1f829aef313bb9ea4c9dfe6bc8fc0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54309
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-17 06:58:46 +00:00
Gabe Black
539aaa4bc3 ext: In sst, don't assume existing imports in python blobs.
When executing blobs of python code in the gem5 sst integration, don't
assume previous blobs have already imported modules. Import them
explicitly instead.

Change-Id: I3aa008ffa092cf8ad82ad057eb73bc9de4bf77c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54308
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-17 06:58:46 +00:00
Gabe Black
3e83208332 ext: Stop using the uninitialized pythonMain in sst.
Import the __main__ module when it's first used.

Change-Id: If800bd575398970faa8cb88072becd3d2b4218c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54307
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-17 06:58:46 +00:00
Gabe Black
7f8bbe01be sim-se: (Re)add support for retrying system calls.
The previous incarnation of this support used faults to make the CPU
reexecute the system call instruction again and again to prevent
emulating/passing through blocking system calls from blocking gem5 as
a whole. That support was accidentally removed a while ago. This new
version suspends the thread context executing the system call, and
periodically wakes it up to retry using a periodically scheduled event.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1123

Change-Id: I155fa8205d7ea45e3d102216aeca6ee1979a522f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54205
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-17 05:45:26 +00:00
Gabe Black
c154888b2a arch,sim-se: Handle syscall retry/suppression in the syscall desc.
Rather than make each ISA include boilerplate to ignore a
SyscallReturn's value when it's marked as suppressed or needing a retry,
put that code into the SyscallDesc::doSyscall method instead.

That has two benefits. First, it removes a decent amount of code
duplication which is nice from a maintenance perspective. Second, it
puts the SyscallDesc in charge of figuring out what to do once a system
call implementation finishes. That will let it schedule a retry of the
system call for instance, without worrying about what the ISA is doing
with the SyscallReturn behind its back.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1123

Change-Id: I76760cba75fd23e6e3357f6169c0140bee3f01b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54204
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-17 05:45:26 +00:00
Giacomo Travaglini
3fba052f3f configs: Remove unused WalkCache models
Change-Id: Iebda966e72b484ee15cbc7cd62256a950b2a90f1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54244
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-16 09:00:53 +00:00
Giacomo Travaglini
d1d90c529c configs: Stop using a PTW cache before L2 in Arm configs
This implementation of a walk cache does not allow to skip walks as it
is a simple cache placed in front of the table walker.
It was meant to provide a faster retrieval of page table descriptors
than fetching them from L2 or memory.

This is not needed anymore for Arm as from [1] we implement
partial translation caching in Arm TLBs.

[1]: JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: I00d44a4e3961e15602bf4352f2f42ddccf2b746b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54243
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-16 09:00:53 +00:00
Gabe Black
b39c106eea ext: Fix compilation of the sst gem5 integration.
Replace the old copied version of gem5's main function with an updated
copy. This fixes compilation, but there's still a problem running an sst
example where there's a segfault inside the python interpreter.

Change-Id: I95714a9264636c14e1dda3174bc0d79e3d881727
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54006
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54266
2021-12-16 01:57:26 +00:00
Gabe Black
7f4a485fcf sim: Make the EmbeddedPyBind::initAll method work correctly.
This method depended on all of the EmbeddedPyBind objects having all
been constructed already so that it would have a complete list. This
would only be true if it was called after static intialization was
complete, which is not true if python is ready to go as soon as gem5
(in library form) is loaded.

This change makes EmbeddedPyBind able to defer initialization of a
module more generically than before, so that they can wait for either
another module to be initiailized, or the _m5 package itself.

Change-Id: I6b636524f969bd9882d8c1a7594dc36eb4e78037
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54005
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54265
2021-12-16 01:57:26 +00:00
Gabe Black
ebbfe1d281 python: Replace PYBIND11_EMBEDDED_MODULE with GEM5_PYBIND_MODULE_INIT.
That will make it possible for gem5's static intializers to run even if
the python interpreter has started.

Change-Id: Ic3574c32244e5ac475222f6d305ddc70dd6298d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54004
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54264
2021-12-16 01:57:26 +00:00
Gabe Black
4f987ff52d python: Add a mechanism for installing pybind modules.
pybind provides a mechanism for this already, but it assumes that
because it works through static initializers, it must run before the
python interpreter has started. That is not true when gem5 is built as a
library, since its static intitializers won't run until that library is
loaded.

Change-Id: I6f36c5f3831dda893039b4923902e9ce46a91808
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54003
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54263
2021-12-16 01:57:26 +00:00
Gabe Black
2a5f2ef55a scons: Make the sim_objects parameter of SimObject mandantory.
If there really are no c++ sim_objects in the file, then sim_objects can
be set to [] which it used to default to.

This way, if someone hasn't remembered to update their SConscript files
for the new sim_objects and enums parameters, this will give them some
indication what's wrong, rather than the build just failing later.

Change-Id: Ic1933f7b9dfff7dd7e403c6c84f1f510c8ee8c72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54203
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-12-15 10:48:03 +00:00
Giacomo Travaglini
ec891adca9 arch-arm: Do not squash table walks if translation is partial
As partial translations have been introduced we cannot just
rely on checking if there is a valid translation when looking
for translations to squash.
The translation has to be complete as well.

This is fixing realview-o3-checker regression

Change-Id: I1ad42bd6172207a72f53b7a843c323c0eea88f06
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54043
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-13 09:22:01 +00:00
Giacomo Travaglini
fcb544d569 arch-arm: Allow the L2 unified TLB to store partial translations
We are allowing the L2 TLB to store partial translations from the
second level of lookup

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: I1286c14a256470c2075fe5533930617139d4d087
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52126
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-12 05:04:24 +00:00
Giacomo Travaglini
6ea9a7fe73 arch-arm: Allowing table descriptor to be inserted in TLB
This patch is modifying both TableWalker and MMU to effectively
store/use partial translations

* TableWalker changes: If there is a TLB supporting partial
translations (implemented with previous patch), the TableWalker will
craft partial entries and forward them to the TLB as walks are performed

* MMU changes: We now instruct the table walker to start a page
table traversal even if we hit in the TLB, if the matching entry
holds a partial translation

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: Id20aaf4ea02960d50d8345f3e174c698af21ad1c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52125
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-12 05:04:24 +00:00
Giacomo Travaglini
49cb833ee6 arch-arm: Allow TLB to be used as a WalkCache
This patch allows partial translation entries (intermediate PAs obtained
from a table walk) to be stored in an ArmTLB. This effectively means
reserving a fraction of the TLB entries to cache table walks

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: Id0efb7d75dd017366c4c3b74de7b57355a53a01a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52124
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-12 05:04:24 +00:00
Gabe Black
8452e7bf19 arch,sim-se: Update the PC before emulating a system call.
For most system calls, it doesn't matter if the PC is advanced to the
instruction after the system call instruction before or after the system
call itself is invoked, because the system call itself doesn't interact
with it.

For some system calls however, specifically "clone" and "execve",
advancing the PC *after* the system call complicates things, because it
means the system call needs to set the PC to something that will equal
the desired value only *after* it's advanced.

By setting the PC *before* the system call, the system call can set the
PC to whatever it needs to. This means the new cloned context doesn't
need to advance the PC because it's already advanced, and execve doesn't
need to set NPC, it can leave the PC set to the correct value from the
entry point set during Process initialization.

Change-Id: I830607c2e9adcc22e738178fd3663417512e2e56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53983
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Kyle Roarty <kyleroarty1716@gmail.com>
2021-12-12 00:29:53 +00:00
Matthew Poremba
9313294efe misc: Remove AMD license addition
Remove the line "For use for simulation and test purposes only" in files
were AMD is the only copyright holder listed in the header. This happens
to be the case for all files where this line exists, removing it
completely from gem5.

Change-Id: I623f266b002f564301b28774f49081099cfc60fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53943
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 04:00:56 +00:00
Andreas Sandberg
d287d8e050 python: Add simulator instantiation checks
Check that m5.instantiate() has been called before m5.simulate() and
that m5.instantiate() is only called once.

Change-Id: Iced129cfd3d09564e2ef619eba829fd294c8a6ac
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53923
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 04:00:06 +00:00
Matthew Poremba
0ae1a9d109 arch-vega: Implement S_SLEEP
This is merely copied from arch-gcn3.

Change-Id: Ibd2bda37fe9adc083a35efab0f59617d386019b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53883
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
23aec13f07 arch-vega: Implement V_AND_OR_B32
Change-Id: I8daeb8de2db5996e132cf7ed729f02c3c94a6862
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53868
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
f1e3fa7a3e arch-vega: Implement V_ADD3_U32
Change-Id: I4d01265f946e289cbff56090c2dd193ea66d5c70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53867
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
2abc51e810 arch-vega: Impelemnt V_ADD_LSHL_U32
Change-Id: Ia4e465ef2534fe28dc846f728b2e1da3dfe4f7d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53866
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
04d025806d arch-vega: Implement V_LSHL_ADD_U32
Change-Id: I986f82e8c6c02b0d62e55fbaed1c3f9e5b2b4a43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53865
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
19788d3b56 arch-vega: Implement V_LSHL_OR_B32
Change-Id: I237410e05df9a96323a6ceb7d09ae2a2a8608f16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53864
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
b5d8d9ddcc arch-vega: Implement V_OR3_B32
Change-Id: Id6c074033b08058b739e056f06b40ee5735f8f00
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53863
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Bobby R. Bruce
6baea72d8e stdlib: Add beta simulate module to the gem5 stdlib
This module is used to semi-automate the running of gem5 simulation,
mostly by handling exit events automatically and removing instantiation
boilerplate code.

NOTE: This module is still in beta.

Change-Id: I4706119478464efcf4d92e3a1da05bddd0953b6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50753
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2021-12-11 03:58:47 +00:00
Bobby R. Bruce
9bd3f9588a tests: Add test for the lupv example
Change-Id: Ib17f59b5b6ab9704be14e73d203bbab61caada90
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53903
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:58:15 +00:00
Bobby R. Bruce
10dcd71716 tests: Add default DRAM class for riscv/x86 boot tests
These scripts can be quite useful for running quick boot tests. However,
having to specify the DRAM each time is laborious. A sensible default
has therefore been set.

Change-Id: I2714b479853f686246383411a46a98494ba617da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53848
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:58:15 +00:00
Bobby R. Bruce
73b59bccd0 configs: Fix terminology to 'ticks' in NPB configs
Instructions was not the correct terminolgy here. It should be ticks.

Change-Id: I08c125049e8dc2cc8c488a820530c6c6a45d7367
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53847
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:58:15 +00:00
Bobby R. Bruce
35f18c4c50 stdlib,configs: Set SPEC examples partition param to optional
The SPEC2006 and SPEC2017 example configs require the passing of SPEC
disk image to function correctly. Prior to this commit a root partition
parameter was required. However, disk images don't necessarily have
partitions. In this case an empty string needed passed.

This patch makes the root partition parameter optional. If a disk image
does not have a root partition, it does not need specified.

Change-Id: Ic0093c70c72ab83ffaca54c8ad24245d84a5e5ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53846
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:58:15 +00:00
Bobby R. Bruce
5622560ce9 stdlib: Add CustomDiskImageResource
This CustomResource can be used to specify a custom, local disk image.
It allows the user to specify the disk root partition parameter
considerably easier than when setting a disk image through a
CustomResource.

Change-Id: I8189ad065124d028aea9fab1c7f07108aa4ce6d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53844
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-10 20:08:11 +00:00
Bobby R. Bruce
69255abeb0 stdlib: Fix CustomResource metadata
CustomResource's base class, AbstractResource, must be constructed with
a dictionary for the 'metadata' field. However, if the user did not
specify any metadata for the CustomResource, None is passed. This is
not permitted and can cause error. This patch ensures the metadata is
set to an empty dictionary by default

Change-Id: I358725ee6982dc9c6410eac3ad8194fa676dd326
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53843
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-10 20:08:11 +00:00
Giacomo Travaglini
ef34cd0a00 arch-arm: Add partial param to TlbEntry
The boolean will flag a partial translation

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: Ia27e321cd5c4b062cafcfd0dc39a208a4d5e3247
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52123
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-10 16:09:09 +00:00
Giacomo Travaglini
db05eb9d89 arch-arm: Use ArmRelease in MMU and TableWalker
Change-Id: I210c73e0e66390f702dad6e7d737c8271b119091
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51408
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 19:21:03 +00:00
Matthew Poremba
c028af111a arch-gcn3,gpu-compute: Move TLB to common folder in amdgpu
This TLB is more of an "APU" TLB than anything GCN3 specific. It can be
used with either GCN3 or Vega. With this change, VEGA_X86 builds and one
can run binaries with Vega ISA code using the same steps as GCN3 but
building the Vega ISA instead.

Change-Id: I0c92bcd0379a18628dc05cb5af070bdc7e692c7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53803
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 17:26:15 +00:00
Giacomo Travaglini
7f2079f662 ext: Avoid content duplication in gem5-SST docs
A brief guide on how to run the gem5 SST example scripts
is already provided in the README file, so there is no need
to copy-paste it in the INSTALL file, which should cover
the building phase only.

Change-Id: I49c677f54450d97a1c8508764e45ab23b4b5fe33
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53629
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 10:49:08 +00:00
Giacomo Travaglini
5e89f1f679 ext: Add an Arm section for gem5-SST README.md
Change-Id: Ia10948a836797855219aef406bf38f52d28d8e26
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53628
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 10:49:08 +00:00
Giacomo Travaglini
12502d2529 ext, configs: Add example Arm gem5 SST platform
JIRA: https://gem5.atlassian.net/browse/GEM5-1121

Change-Id: I7544823710d9a63146d18d4fe9b7c969312ad4d7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53627
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 10:49:08 +00:00
Giacomo Travaglini
85dc34ebf8 ext: Make gem5-SST support CMOs
Change-Id: I45047702018512dfef5a93a633871821f3c69820
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53626
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 10:49:08 +00:00
Giacomo Travaglini
d421e7acd0 ext: Fix segfault in simulate_limit_event shortcut
In the SST integration the top of the main queue is checked
for an event before starting the simulation.

If the first event is scheduled after the ending tick, we are
just returning the simulate_limit_event without entering
the simulation loop.

If the method is called with an empty queue, the following
line will segfault (getHead() == nullptr):

gem5::mainEventQueue[0]->getHead()->when()

With this patch we are covering the case where we have
an empty event queue

Change-Id: I04463b45b269361172a9dd2fe1ba6e9428ac64f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53723
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 10:48:44 +00:00
Bobby R. Bruce
c96409f301 dev: Remove unused private variable in lupio_tmr.hh
This was causing the compiler-checks to fail:
https://jenkins.gem5.org/job/compiler-checks/71

Clang-11 complained of an unused private variable. This variable is
removed in this commit.

Change-Id: I4a43d3cae0fe4ffed4e1df3d94849ac7dc24cc0b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53823
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 00:39:10 +00:00
Kaustav Goswami
99c56f95a6 stdlib,configs: Config added for SPEC CPU2017 using stdlib.
This change adds a config file to execute SPEC CPU 2017 benchmarks
using gem5 stdlib.

Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: I1c4e7cb56e18db44eac5549f9c7ca7379e377e04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53166
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 19:34:00 +00:00
Kaustav Goswami
0830b273cb stdlib,configs: Config added for SPEC CPU2006 using stdlib.
This change adds a config file to execute SPEC CPU 2006 benchmarks
using gem5 stdlib.

Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: I4287433717e4a3d05136b27554accd577275e1be
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53165
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 19:34:00 +00:00
Kaustav Goswami
e2eb6ae20f stdlib,configs: Config added for RISCV boot-test using stdlib.
This change adds a config file to boot Ubuntu-20.04 using RISCV ISA
using gem5 stdlib. It also adds a new test for the same.

Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: Id2b5e46e7ba9e3c4701c97330406537dffa44479
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53024
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 19:34:00 +00:00
Kaustav Goswami
23910fb2d0 stdlib,configs: Adding a config to run GAPBS using stdlib.
This change adds a config file to execute GAPBS benchmarks using
gem5 stdlib. It also adds a new test for the same.

Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: I10326cace4e6fa160e02e479fb4443277af3966f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53023
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 19:34:00 +00:00
Kaustav Goswami
84cd82f139 stdlib,configs: Adding a config to run NPB using stdlib.
This change adds a config file to execute NPB benchmarks using
gem5 stdlib. Also, it adds a new test for the same.

Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: I527b7d12be7ab43e61dde507095ebf9fa4b44867
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52964
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 19:34:00 +00:00
Kaustav Goswami
1f88d699f1 stdlib,configs: Adding a config to run PARSEC using stdlib.
This change adds a config file to execute PARSEC benchmarks using
gem5 stdlib. It also adds a new test for the same.

Change-Id: I2dfaae388f4a697911ef7894b35f7bfccd7e4761
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52943
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 19:34:00 +00:00
Matthew Poremba
85eaf9c799 arch-gcn3: Delete extraneous registers header
This file is a duplicate of arch/amdgpu/gcn3/gpu_registers.hh and is in
the wrong location. It should be removed to avoid mistakenly editing the
wrong file.

Change-Id: Ie96e22fe8f78fda954af788b472ec2df4782e4a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53743
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-12-08 14:59:53 +00:00