The only part of the MaserPort the PortProxy uses is the sendFunctional
function which is part of the functional protocol. Rather than require
a MasterPort which comes along with a lot of other mechanisms, this
change slightly adjusts the PortProxy to only require that function
through the use of a delegate. That allows lots of flexibility in how
the actual packet gets sent and what sends it.
In cases where code constructs a PortProxy and passes its constructor
an unbound MasterPort, the PortProxy will create a delegate to the
sendFunctional method on its own.
This should also make it easier for objects which don't have
traditional gem5 style ports, for instance systemc models, to implement
just the little bit of the protocol they need, rather than having to
stub out a whole port class, most of which will be ignored.
Change-Id: I234b42ce050f12313b551a61736186ddf2c9e2c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20229
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The void * type is for pointers which point to an unknown type. We
should use that when handling anonymous buffers in the PortProxy
functions, instead of uint8_t * which points to bytes.
Importantly, C/C++ doesn't require you to do any casting to turn an
arbitrary pointer type into a void *. This will get rid of lots of
tedious, verbose casting throughout the code base.
Change-Id: Id1adecc283c866d8e24524efd64f37b079088bd9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18571
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The idea of a "secure" memory area/access is specific to ARM and
shouldn't be in the common mem directory, although it's built in to the
generic memory protocol at this point.
Regardless, it should minimially be in its own file like the virtual
and physical port proxy classes are.
Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
These selected their behavior based on ifdefs and had to be disabled
when on the NULL ISA. The versions which take an explicit endianness
have been renamed to just read/write instead of readGtoH and writeHtoG
since the direction of the translation is obvious from context.
Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The current physical port proxy doesn't know how to tag memory
accesses as secure. Refactor the class slightly to create a set of
methods (readBlobPhys, writeBlobPhys, memsetBlobPhys) that always
access physical memory and take a set of Request::Flags as an
argument. The new port proxy, SecurePortProxy, uses this interface to
issue secure physical accesses.
Change-Id: I8232a4b35025be04ec8f91a00f0580266bacb338
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8364
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
This patch changes the various write functions in the port proxies
to use const pointers for all sources (similar to how memcpy works).
The one unfortunate aspect is the need for a const_cast in the packet,
to avoid having to juggle a const and a non-const data pointer. This
design decision can always be re-evaluated at a later stage.
This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.
--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.
Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.
A follow-on patch updates the configuration scripts accordingly.
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
This is a trivial patch that merely makes all the member functions of
the port proxies const. There is no good reason why they should not
be, and this change only serves to make it explicit that they are not
modified through their use.
This patch moves the readBlob/writeBlob/memsetBlob from the Port class
to the PortProxy class, thus making a clear separation of the basic
port functionality (recv/send functional/atomic/timing), and the
higher-level functional accessors available on the port proxies.
There are only a few places in the code base where the blob functions
were used on ports, and they are all for peeking into the memory
system without making a normal memory access (in the memtest, and the
malta and tsunami pchip). The memtest also exemplifies how easy it is
to create a non-translating proxy if desired. The malta and tsunami
pchip used a slave port to perform a functional read, and this is now
changed to rely on the physProxy of the system (to which they already
have a pointer).
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
