Commit Graph

19012 Commits

Author SHA1 Message Date
Jason Lowe-Power
8e8c1ded15 scons: Update enum output when not using python
This changeset brings the enum_cc.py file in line with how the
sim_object_param_struct_cc.py file works and updates the SConscript to
correctly tag the created source files.

Change-Id: I4635a4f46de7d62a6c38e71ace121c06e139d486
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59609
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-05-19 14:32:11 +00:00
Jason Lowe-Power
e8e0a2ed06 util,systemc: Update systemc connection
Change-Id: I5b5c7de9e734dd8a58160193d68c9a13d649b739
Issue-On: https://gem5.atlassian.net/browse/GEM5-1218
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59589
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-19 14:32:06 +00:00
Giacomo Travaglini
128b78177c configs: Add --enable-dvm CL option to CHI configs
By using the "--enable-dvm" command line option it is possible
to issue DVM messages from Arm CPUs

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I0a2b683ad3403590515bd406e241b66961cee964
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57301
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-18 09:16:17 +00:00
Samuel Stark
38d360a475 configs, mem-ruby: Implement DVMOps in CHI
1) Handling TLBI/TLBI_SYNC requests from the PE in the CHI Request Node
(Generating DVMOps)

2) Adding a new machine type for the Misc Node (MN) that handles DVMOps
from the Request Node (RN), following the protocol specified within
the Amba 5 CHI Architecture Specification [1]

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

[1]: https://developer.arm.com/documentation/ihi0050/latest

Change-Id: I9ac00463ec3080c90bb81af721d88d44047123b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57298
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-18 08:52:53 +00:00
Matthew Poremba
1e6ff02c25 dev-amdgpu: Allow for atomics in SystemHub
It seems that applications can be compiled which issue atomics to host
memory, such as heterosync. Remove the arbitrary assert to disallow them
and issue atomics as a DMA write by default.

Change-Id: I7812a421a9312406b3faccdc05d6c7e9fc837da0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59669
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-16 15:08:09 +00:00
Matthew Poremba
49c6e2fb48 configs: Add example scripts for HIP apps for GPUFS
This adds configuration scripts to run the HIP cookbook, HIP samples,
and HIP versions of rodinia 3.0.

Cleaned up the other vega10_kvm example script.

Change-Id: I26de50426e7e68741b13de0c4b15b08f0789a062
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59670
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-16 15:07:55 +00:00
Bobby R. Bruce
45e6e57b5a stdlib: Implicitly determine FS/SE mode via workload
Setting whether FS or SE mode is to be used explicitly is not necessary
as we can determine this depending on what kind of workload is set.

Change-Id: Icc0ac749df231eaa9af8ba2363b466fcb405ccea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59571
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-13 19:04:21 +00:00
Matthias Jung
f355f1f258 systemc: Fixed Bug in SystemC Example
Change-Id: I857a181470a491874c8ab9f7d467c89dafd97e6e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59550
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-13 18:49:58 +00:00
Matthias Jung
4bc5efbc37 systemc: Simple TLM Example added
Change-Id: I2cb0c95773b8c6d15ffdffffaafbe3133a392a54
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59549
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-05-13 18:49:48 +00:00
Gabe Black
3d5bb844ee python: Don't assume RubyNetwork exists in do_ruby_dot.
If Ruby is disabled, then RubyNetwork is not a SimObject, and
do_ruby_dot which tries to reference it will crash. This more flexibly
checks for RubyNetwork, and if that isn't in m5.objects will gracefully
return instead of crashing.

Also streamline the code in that function a little bit using filter()
instead of preconstructing the list of ruby networks.

Change-Id: Ia4bdb04201df8453a1b6692a2f211b6cde00be2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59629
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-13 08:09:19 +00:00
Bobby R. Bruce
ed6c57e4ab tests,arch-arm: Add guards for ARM-specific test
The nightly tests, https://jenkins.gem5.org/job/nightly/219/, were
failing with the following error when running build/NULL/unittests.opt:

```
[ENUMDECL] m5.objects.ArmSystem, ArmExtension -> NULL/enums/ArmExtension.hh
terminate called after throwing an instance of 'pybind11::error_already_set'
  what():  ModuleNotFoundError: No module named 'm5.objects.ArmSystem'
At:
  <frozen importlib._bootstrap>(973): _find_and_load_unlocked
  <frozen importlib._bootstrap>(991): _find_and_load
  <frozen importlib._bootstrap>(1014): _gcd_import
  /usr/lib/python3.8/importlib/__init__.py(127): import_module
  build_tools/enum_hh.py(58): <module>
Aborted (core dumped)
scons: *** [build/NULL/enums/ArmExtension.hh] Error 134
```

The reason for this is the 'aapcs64.test' now transitively includes the
'ArmExtension' enum via this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/59471.

As this test now only works with the ARM ISA, a guard has been included.
As noted in the comment, GTest does not have the 'tags' parameter so the
'TARGET_ISA' environment variable was used. This will need updated when
the multi-isa code is incorporated.

Change-Id: I2793094bf7c813afd97933750332fa3f3b7bd8dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59569
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-11 19:27:33 +00:00
Richard Cooper
b1d10aa7b6 misc: Update Dmesg dump for changes to printk in Linux v5.10+.
The Linux Kernel's printk mechanism and data structures were
overhauled in v5.10. This patch updates gem5's facility to dump the
kernel Dmesg buffer on kernel panic to account for these changes.

The new mechanism splits the Demsg ringbuffer into three separate
ringbuffers, one containing the message data, one containing
descriptors used for lock-free synchronisation, and one containing the
message infos. For a detailed description please see the header of
`kernel/printk/printk_ringbuffer.c` in the Linux source code.

The new gem5 implementation tests for the correct version to
run (pre-v5.10 or post-v5.10) by testing for the presence of symbols
in the kernel. The new, post-v5.10 dump code is templated on types
compatible with the kernel's atomic_long_t to account for differences
between the 64-bit and 32-bit Linux kernels.

Because the new Dmesg buffer dump code in gem5 is intended for
disaster recovery, it intentionally prints the full Dmesg buffer with
minimal checking of the validity of the messages. Partially finished
and/or uncommitted messages will be printed along with the finalised
messages.

Change-Id: I62ac20735e0679f1ba2062ca7bb13692a5ca1eae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59509
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-05-11 13:27:50 +00:00
Giacomo Travaglini
1455ac0e0c arch-arm: Turn on EL2/EL3 support by default in ArmSystem
In order to turn them off a user needs to explicitly do so
by providing a different ArmRelease objec

Change-Id: I227cee80c5517cdd50cf07c62d9a131ce261310f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51011
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-11 13:00:42 +00:00
Giacomo Travaglini
99d2348910 system-arm: Awake GICv3 reditributors in the bootloader
Part of the booting procedure should be to wake up every redistributor
in the system by setting GICR_WAKER.Processor sleep to 0

Change-Id: I27150a812639de48c4ae0a4decabb4e414fa3a09
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59395
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-10 08:21:52 +00:00
Giacomo Travaglini
3fec0f9ca3 system-arm: Detect the GICv3 redistributor stride at runtime
Some platforms are not GICv4 compatible, therefore we need to make sure
the stride between redistributors is configurable:

2 frames of 64KiB for GICv3 => a stride of 128KiB
4 frames of 64KiB for GICv4 => a stride of 256KiB

We detect this at runtime by reading the GICD_PIDR2.ArchRev bitfield
This is 3 for GICv3 and 4 for GICv4.

Note: other software projects [1] rely on a different check, mainly
reading the GICR_TYPER.VLPIS bit
We diverge from this behaviour as VLPIS are not implemented and we do
not want to incorrectly report this to the probing software.

We should move to VLPIS once they get implemented

[1]: https://github.com/torvalds/linux/blob/\
    107c948d1d3e61d10aee9d0f7c3d81bbee9842af/\
    drivers/irqchip/irq-gic-v3.c#L864

Change-Id: I7cc554f48cc6a347c03ed80cf2ea320f618a59c2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59394
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-10 08:21:18 +00:00
Bobby R. Bruce
90bb4cbebb tests: Fix docker '--memory' flag in GPU test
A missing space was resulting in an error:

```
invalid argument "18ghacc-test-weekly" for "-m, --memory" flag: invalid size: '18ghacc-test-weekly'
```

Change-Id: I63cd3f1cf877442b1b5fffc0a09024ca6ae94436
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59489
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-05-10 00:48:47 +00:00
Gabe Black
67f1ec7f5b fastmodel: Make ArmFastModelComponent-s take a tags parameter.
ArmFastModelComponents must *minimally* be guarded by "arm fastmodel"
tags, but may actually be covered by a more specific tag which is a
subset of "arm fastmodel", for instance if they are controlled by a
kconfig variable and may or may not be included in "gem5 lib"
independently of other sources which are part of "arm fastmodel".

The contents set up by ArmFastModelComponent are already guarded by a
fixed tag, so this change just needs to plumb through the tag as
specified when the ArmFastModelComponent is created instead.

Change-Id: I619c31107acda378a5439718e32938843f024e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59473
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-09 20:05:32 +00:00
Giacomo Travaglini
fd250dbed3 arch-arm: Consolidate Arm FEAT check into single hasExtension
There's no need to have a per extension helper function now
that we rely on ArmExtension objects

We are therefore removing:

* HavePACExt
* HaveLVA
* HaveSecureEL2Ext
* HaveVirtHostExt

Change-Id: I2094c1eb6310506787e5628aa62d0b14e917ab5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59471
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-09 16:45:58 +00:00
Giacomo Travaglini
6412be29f4 arch-arm: Check implemented features through the release object
This is faster than going through the ISA and reading the corresponding
ID register value

Change-Id: Iec247167f3b99dcabf2908fceb0c2365c37ba017
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59470
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-09 16:45:58 +00:00
Giacomo Travaglini
20e1ade7ed arch-arm: Do not read SCR on the critical path
Change-Id: I0318563382b3c910c599f9fa16ad29553129c537
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59469
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-09 16:45:58 +00:00
Angie Lee
a8e8d64e5d fastmodel: Fix an index parsing bug on PL330::gem5_getPort
Change-Id: I2cf1abb0eb21c6bd65f81628be52650ef9250fbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59369
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-09 08:47:45 +00:00
Gabe Black
dfc8614ee2 scons: Ensure config file values are strings.
Apparently, sometimes a SCons Value node created with an integer value
0 will have a string representation which is the empty string, which
is obviously problematic. To work around this bug, convert the value
to a string explicitly before creating the Value node, so that we get
a sensible translation instead.

Change-Id: I4a09b2fb366aaf2d4d1c7e6f8cc84224b2d010c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59472
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-05-09 02:55:52 +00:00
Giacomo Travaglini
4ccb2643c1 base: clang-7 can't deduce non type parameter with auto
We now use explicit types instead (size_t)
This is fixing compiler checks, build 224 [1]

[1]: https://jenkins.gem5.org/job/compiler-checks/224/\
    artifact/compile-test-out/clang-version-7/

Change-Id: I5e94652b2fef554b1c47ce2972462401703ca5d5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59430
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-05-08 08:00:05 +00:00
Giacomo Travaglini
150d7a03bd base: Fix -Werror=unused-variable in Memoizer
Change-Id: I222a445121a35a4abc1a3fa2068e6c26ad7ee843
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59429
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-05-08 08:00:05 +00:00
Giacomo Travaglini
446c0ff6ba system-arm: Fix GICv3 in multi-cluster configuration
Current way of initializing GICv3 in the gem5 bootloader doesn't
work when there is a PE labelled with non-zero Aff1, Aff2 or Aff3
in the MPIDR_EL1 register
(For example in a multi-cluster configuration).

This is because the bootloader is considering Aff0 only

mrs x0, mpidr_el1
// extract the primary CPU.
ldr x1, =0xff00ffffff
and    x2, x0, #0xff // use Aff0 as cpuid for now...

With this patch we are solving the issue, by considering
every affinity number. Now the primary cpu is the cpu with

Aff3..Aff0 = 0.

The bootloader was also using Aff0 (stored in x2, see above)
to let every CPU index their own redistributor memory mapped frames.
In this model every secondary CPU was in charge of initializing
their own redistributor registers.

This can't be used anymore as we have a tuple of affinity
numbers now rather than a single flat index.

We are addressing the issue by letting the primary cpu initialize
every redistributor in the system. This is done by iterating
over consecutive frames and by reading GICR_TYPER.Last, which
is set to 1 if the current frame is the last one.

Change-Id: I2bcad286c2282bf1c47618e5391bf1c2e2b27013
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59393
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-07 22:41:12 +00:00
Giacomo Travaglini
5d45c50b48 misc: Add VExpress_GEM5_Foundation bootloader
The VExpress_GEM5_Foundation platform cannot use the VExpress_GEM5_V2
bootloader as the GIC has a different memory map

A new tarball has been uploaded to dist.gem5.org with the new bootloader

Change-Id: Ie0c16e623c3323b7be2a333cd6b0ffcf891b7b9b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59392
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-07 22:40:47 +00:00
Giacomo Travaglini
776321d2c2 dev-arm: GICD_PIDR2.ArchRev value depends on GIC version
The GIC architecture specification states the GICD_PIDR2.ArchRev
field is set to 3 for GICv3 and to 4 for GICv4. We bind this
value to the gicv4 parameter

Change-Id: I3ba34bc0b4538b4d5170915a4ee042e534f2590f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59391
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-07 22:40:25 +00:00
Matthew Poremba
54d2438066 dev-amdgpu: Removed hardcoded AQL queue size
The AQL queue size is currently hardcoded to 64kB. For longer running
applications this causes the circular queue to wrap before reaching the
real end of the queue. Add the computation for queue size instead.

Previously longer applications (e.g., bc in pannotia) were hanging
around 4k kernels. With change the application launches 10k+ kernels.

Change-Id: I6c31677c1799a3c9ce28cf4e7e79efcb987e3b7f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59449
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2022-05-07 03:47:06 +00:00
Bobby R. Bruce
4119529d8a util-docker: Fix the broken riscv cross-compiler docker
Previously the line
```
RUN git checkout --recurse-submodules 051b9f7ddb7d136777505ea19c70a41926842b96
```

Was causing an error.

Change-Id: Ia13e676f7113c320d4a335b4999c47de415b278b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59351
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2022-05-06 20:53:32 +00:00
Bobby R. Bruce
92894edf78 util-docker: Ensure all apt update/upgrade/install in one RUN
Prior to this patch those building from these Dockerfiles could
encounter caching issues where the `apt -y update` RUN was loaded from a
cached layer prior to running the `install` command. Typically this was
trying to obtain a package from a wrong IP address. The fix for this is
to run this all in one Docker RUN to avoid loading a broken cache.

Change-Id: If309c5c1d4a0240fed670abe980772d90f7d2172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59350
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-06 20:53:32 +00:00
Bobby R. Bruce
a13e9bd4f7 util-docker: Add gpu-fs to docker-compose.yaml
Though https://gem5-review.googlesource.com/c/public/gem5/+/59051 added
the gpu-fs image, it needs added to the docker-compose.yaml file to be
automatically build and pushed to our docker image repository.

With this patch a user can execute `docker-compose build gpu-fs` to
build this image locally.

Change-Id: Iacc768d3d1b7fccb8867e8c788012c292216cb02
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59349
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-06 20:53:32 +00:00
Giacomo Travaglini
7a9e99400f dev-arm: Gicv3.gicv4 parameter set to False by default
GICv4 features are not currently implemented so it is more natural
to set it to false by default

VExpress_GEM5_V2 platform assumes a GICv4 memory map therefore
sets it to True

Change-Id: Ib4bd17acd56cd029aacf5578ab0259a6ea1bb30c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59390
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-06 16:29:22 +00:00
Giacomo Travaglini
36c4778c7d system-arm: Do not trap SVE instructions to EL3
While other CPTR_EL3 bitfields disable trapping by setting
them to zero, SVE trapping works in the opposite way round:

we need to set CPTR_EL3.EZ to 1 if we don't want an EL3 trap

Change-Id: I97d396c402a6d7ebda40d6787ee2f41499f2d1c5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59389
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-06 16:29:12 +00:00
Bobby R. Bruce
6209641d33 tests: Disable 2 core Timing MESI_Two_Level X86 boot test
This is due to this error: https://gem5.atlassian.net/browse/GEM5-1219.
After several weeks of failing Weekly tests, this test will be disabled
until it can be fixed.

Change-Id: If7510426c33f3412a559681f653e955409fcdce4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59329
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-05-05 23:39:09 +00:00
Matthew Poremba
c170994676 dev-amdgpu: Fix size issue in interrupt handler
The data allocated for the DMA request used to send an interrupt cookie
was too large. This was causing the memcpy to occasionally seg fault due
to reading past the bounds of the source parameter (the interrupt cookie
struct). Correct the size and add a compile time check to ensure it is
the correct number of bytes expected by the driver.

Change-Id: Ie9757cb52ce8f72354582c36cfd3a7e8a1525484
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58969
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-05-05 16:09:49 +00:00
Matt Sinclair
11ccc87c91 tests, gpu-compute, mem-ruby: add GPU Ruby random test to nightly
Add a longer test for the GPU Ruby random tester to the nightly
regression.  This test is sized to take approximately 30 minutes
while providing more coverage than the per check-in Ruby random test,
which takes 30 seconds.

Change-Id: I398feb1283b24f801275ba13d6c53d236849f2eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59272
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-04 20:57:45 +00:00
Giacomo Travaglini
7580e8d53d arch-arm: Memoize computeAddrTop in the MMU code
Profiling gem5 has indicated computeAddrTop as one of the main
contributors in AArch64 simulation time

The utility function gets used in the critical path of gem5, which is
the memory translation subsystem. The function is supposed to compute a
rather trivial task: identifying the "real" most significant bit of a
virtual address.

This turns out to be quite expensive. Why?

The main issue is the AArch32/AArch64 check, which uses the ELIs32
helper. This performs a sequential read of several MiscReg
values until it confirms that an EL is indeed using AArch32 (or
AArch64).

This is functionally accurate but it is too expensive for the critical
path of a program.

This patch is addressing the issue by adding a Memoizer object for the
computeAddrTop function to the CachedState data structure, which is
already holding cached system register values for performance reasons.
Whenever we need to invalidate those sys reg values because of a change
in the translation system, we also flush/invalidate the memoizer cache

Change-Id: If42e945c650c293ace304fb4c35e709783bb82d4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59151
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-04 14:04:56 +00:00
Bobby R. Bruce
cc6aa4c173 tests: Add tests for the resource downloader
Change-Id: Ibc2685670dc50234b9b216226c03ed24c8bc9925
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59089
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-03 19:22:57 +00:00
Bobby R. Bruce
e552295620 stdlib: Allow JSON resources file to be set via env-var
Via the "GEM5_RESOURCE_JSON" environment variable, a user can override
the the default resources.json retrieval location. E.g., a user can have
their own resources.json file and load it instead. This may be a local
file path or a URL.

Code has been changed in downloader.py to allow the loading of
resources.json from either a URL or a local file path. Previously only
URLs were valid.

Change-Id: I022eee58efadc4819069563e9046ce9d84e5cf06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59069
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-03 19:22:57 +00:00
Bobby R. Bruce
d5ebbc1857 stdlib: Update the resources.json URL
It is important this URL remains stable across releases. Pulling
directly from the Google Source git repo is not stable and may change
over time. This patch updates the URL to
https://resources.gem5.org/resources.json. As the gem5.org domain is
under the gem5 project's control, we can ensure this does not change.

Change-Id: I549fabb1525ee1df68cb1641c1bd82ea8bd32262
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59050
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-03 19:22:57 +00:00
Hoa Nguyen
46266596ff arch-arm,cpu: Move KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 check to Kvm
This change [1] requires performing KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 check.
However, checkExtension() is only available within the Kvm class and
the KvmVM class.

A new function, Kvm::capIRQLineLayout2(), is added for checking the
status of KVM_CAP_ARM_IRQ_LINE_LAYOUT_2.

This fixes a compilation error on Arm systems.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/55964

Change-Id: Ia190e06ab451e0ff8d1c4833cd23b7de8852c6dd
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59310
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-05-03 17:09:05 +00:00
Hoa Nguyen
2938119f97 arch-arm: Fix GenericTimer param name in BaseArmKvmCPU
Per change [1], the new name for `int_virt` is `int_el1_virt`.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/58109

Change-Id: Idde4ac831c7a323b80272642e6a48b1c5e488135
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59309
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-05-03 17:09:05 +00:00
Giacomo Travaglini
9c9b3a5e3d arch-arm: Split purifyTaggedAddr in two sub-functions
This patch is splitting the purifyTaggedAddr helper in two
by introducing the maskTaggedAddress utility

* The first part computes the top bit of the address (computeAddrTop)
(This is required as the MSBs of a VA could be used to store
tags like in FEAT_Pauth)

* The second part applies some masking to the supplied
address (maskTaggedAddress) depending on the top bit to
purify the VA from the TAG

The motivation of this split will be clear in the next patch:
we want to memoize the expensive computeAddrTop. Memoizing
purifyTaggedAddr is inefficient as the first argument
is the VA of the memory request so multiple memory requests
will allocate multiple entries in the results cache and
memoization will rarely be used.

We will memoize the VA agnostic computeAddrTop instead

Change-Id: Ib3d8bb521be67a1f21c0891e753396299adf500b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59150
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-03 10:40:19 +00:00
Giacomo Travaglini
05cf88e7c2 base: Add generic Memoizer class
This class implements a generic memoization object:

It takes a function as a constructor argument and memoizes
it. Every time the function gets invoked through the Memoizer object
the result gets saved in the internal cache, ready
to be retrieved next time an invokation is made with the same
arguments.

Example usage:

int fibonacci(int n);

Memoizer fibonacci_memo(fibonacci);
fibonacci_memo(5);

There are two ways to discard a memoization

1) Delete the Memoizer object
2) Use the Memoizer::flush method

In some cases there is little or no reason to discard a memoization
(like in the fibonacci example, where fibonacci(k) always returns
the same value for the same input k)
The memoizer could be used in more complex cases, where a change in
the global state affects the output of the function, which
effectively invalidates the cached results.
It is up to the client to understand when memoization is no longer
valid and to flush the result cache as a consequence.

Change-Id: I6cf496b2aef5a66f5375a627165b2cb2e3a1bfc2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59149
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2022-05-03 10:40:19 +00:00
Srikant Bharadwaj
949e071cec configs: Python 3.2+ requires additional flag for makedirs
makedirs requires and additional flag for makedirs to ignore
error when the directory exists. This change enables overwriting
on existing output directories for a simulation.
https://docs.python.org/3/library/os.html

Change-Id: I1c7329ded1f5eef2c882e3224457e1d991d074fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58190
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-29 22:42:55 +00:00
Giacomo Travaglini
287bea8a4d arch-arm: PAuth inst disassembled with a capitalized first letter
This is not aligned with what we do for other Arm instructions.
This patch removes capitalization of the first letter:

Example

Xpaclri -> xpaclri

Change-Id: I04b3d3b386e34e1dceec940af7c43fc42f538722
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59229
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-04-29 09:15:46 +00:00
Yu-hsin Wang
1f713320fe dev: Expose ResetRequestPort constructor
Port::Port is in protected scope. ResetRequestPort should expose the
constructor by itself.

Change-Id: I72ce701fca89379f90e212d7411f481ae1e1977a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59209
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2022-04-29 02:42:54 +00:00
Bobby R. Bruce
d5da783d75 util: Remove util/stats directory
This does not appear to be used, we are therefore removing it.

Change-Id: I7c99f2e9879efc467bb75e279c4ef3b92fb1aa68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47025
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-28 20:53:42 +00:00
Kaustav Goswami
fda07590df cpu: nullptr in a DPRINTF statement
This change fixes the crashing of gem5 when `Branch` debug flag
is enabled. A DPRINTF statement had a nullptr. This change
prints `INVALID_TARGET` if the nullptr is encountered.

Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: I40bd42c07de25a493a3dd1094a2fd8cc0ce0a79b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59109
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-04-28 16:57:59 +00:00
Giacomo Travaglini
f8589a4719 sim, arch-riscv: Remove Fault debug flag
There is already a Faults debug flag used by Arm and X86 so
having both Fault and Faults is highly confusing

Change-Id: Id5c17f19b51c6257dfc470d07ba050a9de7a9db3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59152
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-04-28 08:52:49 +00:00