Added a parameter to kernel_disk_workload which allows users to change the disk device location. Maintained the previous way of setting a disk device as the default, however added a function to allow users to override this default
The MMIO trace contains register values for parts of the GPU that are
not modeled in gem5, such as registers related to the graphics core.
Since MI100 and MI200 do not have anything that is not modeled, the
MMIO trace is not needed, therefore it does not need to be used or
checked and the command line option goes away entirely for MI100/200.
Change-Id: I23839db32b1b072bd44c8c977899a99347fc9687
Starting with ROCm 5.4+, MI100 and MI200 make use of the translate
further bit in the page table. This bit enables mixing 4kiB and 2MiB
pages and is functionally equivalent to mixing page sizes using the
PDE.P bit for which gem5 currently has support.
With PDE.P bit set, we stop walking and the page size is equal to the
level in the page table we stopped at. For example, stopping at level
2 would be a 1GiB page, stopping at level 3 would be a 2MiB page.
This assumes most pages are 4kiB.
When the F bit is used, it is assumed most pages are 2MiB and we will
stop walking at the 3rd level of the page table unless the F bit is set.
When the F bit is set, the 2nd level PDE contains a block fragment size
representing the page size of the next PDE in the form of 2^(12+size).
If the next page has the F bit set we continue walking to the 4th level.
The block fragment size is hardcoded to 9 in the driver therefore we
assert that the block fragment size must be 0 or 9.
This enables MI200 with ROCm 5.4+ in gem5. This functionality was
determine by examining the driver source code in Linux and there is no
public documentation about this feature or why the change is made in or
around ROCm 5.4.
Change-Id: I603c0208cd9e821f7ad6eeb1d94ae15eaa146fb9
This SDMA packet is much more common starting around ROCm 5.4.
Previously this was mostly used to clear page tables after an
application ended and was therefore left unimplemented. It is
now used for basic operation like device memsets.
This patch implements constant fill as it is now necessary.
Change-Id: I9b2cf076ec17f5ed07c20bb820e7db0c082bbfbc
When using the new operator, delete should be called
on any allocated memory after it's use is complete.
Change-Id: Id5fcfb264b6ddc252c0a9dcafc2d3b020f7b5019
A previous change added a vop2Helper to remove 100s of lines of common
code from VOP2 instructions related to processing SDWA and DPP support.
That change inadvertently changed the type of operand source 0 from
const to non-const. The vector container operator[] does not allow
reading a scalar value such as a constant, a dword literal, etc. The
error shows up in the form of: assert(!scalar) in operand.hh.
Since the SDWA and DPP cases need to modify the source vector and
non-SDWA/DPP cases might require const, we make a non-const copy of the
const source 0 vector and place it in a temporary non-const vector. This
non-const vector is passed to the lambda function implementation of the
instruction. This prevents needing a const and non-const version of the
lambda and avoids needing to propagate the template parameters through
the various SDWA/DPP helper methods which seems like it will not work
anyways as they need to modify the vector.
As a result of this, as more VOP2 instructions are implemented using
this helper, they will need to specify the const and non-const template
parameters of the vector container needed for the instruction.
Change-Id: Ia0b3c550d7de32b830040007a110f4821e3385aa
When using the new operator, delete should be called
on any allocated memory after it's use is complete.
Change-Id: Id5fcfb264b6ddc252c0a9dcafc2d3b020f7b5019
In "src/cpu/testers/gpu_ruby_test" a random number generator was used.
This was using the CPP "<random>" library. This patch changes it to the
gem5 random class (that declared in "base/random.hh").
In addition to this, undeterministic behavior has been removed. Via
"protocol_tester.cc" the RNG is either seeded with a seed specified by
the user, or goes with the gem5 default seed. This ensures reproducable
runs. Prior to this patch the RNG was seeded with `time(NULL)`. This
made finding faults difficult.
This, at least partially, addresses Issue #138
Change-Id: Ia8e9f7b87e91323f828e0b7f6c3906c0c5793b2c
arch-x86: Move CPUID values to python
CPUID values for X86 are currently hard-coded in the C++ source file.
This makes it difficult to configure the bits if needed. Move these to
python instead. This will provide a few benefits:
1. We can enable features for certain configurations, for example AVX
can be enabled when the KVM CPU is used, but otherwise should not be
enabled as gem5 does not have full AVX support.
2. We can more accurately communicate things like cache/TLB sizes based
on the actual gem5 configuration. The CPUID values are can be used by
some libraries, e.g., MPI, to query system topology.
3. Enabling some bits breaks things in certain configurations and this
can be prevented by configuring in python. For example, enabling AVX
seems to currently be breaking SMP, meaning gem5 can only boot one CPU
in that configuration.
In "src/cpu/testers/gpu_ruby_test" a random number generator was used.
This was using the CPP "<random>" library. This patch changes it to the
gem5 random class (that declared in "base/random.hh").
In addition to this, undeterministic behavior has been removed. Via
"protocol_tester.cc" the RNG is either seeded with a seed specified by
the user, or goes with the gem5 default seed. This ensures reproducable
runs. Prior to this patch the RNG was seeded with `time(NULL)`. This
made finding faults difficult.
Change-Id: Ia8e9f7b87e91323f828e0b7f6c3906c0c5793b2c
A previous change added a vop2Helper to remove 100s of lines of common
code from VOP2 instructions related to processing SDWA and DPP support.
That change inadvertently changed the type of operand source 0 from
const to non-const. The vector container operator[] does not allow
reading a scalar value such as a constant, a dword literal, etc. The
error shows up in the form of: assert(!scalar) in operand.hh.
Since the SDWA and DPP cases need to modify the source vector and
non-SDWA/DPP cases might require const, we make a non-const copy of the
const source 0 vector and place it in a tempoary non-const vector. This
non-const vector is passed to the lambda function implementation of the
instruction. This prevents needing a const and non-const version of the
lambda and avoids needing to propagate the template parameters through
the various SDWA/DPP helper methods which seems like it will not work
anyways as they need to modify the vector.
As a result of this, as more VOP2 instructions are implemented using
this helper,they will need to specify the const and non-const template
parameters of the vector container needed for the instruction.
Change-Id: Ia0b3c550d7de32b830040007a110f4821e3385aa
This change syncs the repo's contributing documentation with that of the
website's contributing documentation:
https://www.gem5.org/contributing
From now on we'll attempt to keep the repo's CONTRIBUTING.md
documentation in sync with that on the website.
Change-Id: I2c91e6dd5cd7a9b642377878b007d7da3f0ee2ad
AVX is a requirement for some ROCm libraries, such as rocBLAS, which are
themselves requirements for libraries higher up the stack like PyTorch.
This patch sets the necessary CPUID bits in the GPUFS config to enable
AVX, AVX2, and various SSE features so that applications using these
libraries do not cause an illegal instruction trap.
Change-Id: Id22f543fb2a06b268271725a54075ee6a9a1f041
The extended state CPUID function is used to set the values of the XCR0
register as well as specify the size of storage for context switching
storage for x87 and AVX+. This function is iterative and therefore
requires (1) marking it as such in the hsaSignificantIndex function (2)
setting multiple sets of 4-tuples for the default CPUID values where the
last 4-tuple ends with all zeros.
Change-Id: Ib6a43925afb1cae75f61d8acff52a3cc26ce17c8
Related to the recent changes with moving CPUID values to python, this
value is needed to enable AVX and needs a way to be exposed to python as
well in order to set the bit and the corresponding CPUID values at the
same time.
Change-Id: I3cadb0fe61ff4ebf6de903018a8d8a411bfdb4e0
Various CPUID functions will return different values depending on the
value of ECX when executing the CPUID instruction. Add support for this
in the X86 KVM CPU. A subsequent patch will add a CPUID function which
requires iterating through multiple ECX values.
Change-Id: Ib44a52be52ea632d5e2cee3fb2ca390b60a7202a
CPUID values for X86 are currently hard-coded in the C++ source file.
This makes it difficult to configure the bits if needed. Move these to
python instead. This will provide a few benefits:
1. We can enable features for certain configurations, for example AVX
can be enabled when the KVM CPU is used, but otherwise should not be
enabled as gem5 does not have full AVX support.
2. We can more accurately communicate things like cache/TLB sizes based
on the actual gem5 configuration. The CPUID values are can be used by
some libraries, e.g., MPI, to query system topology.
3. Enabling some bits breaks things in certain configurations and this
can be prevented by configuring in python. For example, enabling AVX
seems to currently be breaking SMP, meaning gem5 can only boot one CPU
in that configuration.
Change-Id: Ib3866f39c86d61374b9451e60b119a3155575884
This change syncs the repo's contributing documentation with that of the
website's contributing documentation:
https://www.gem5.org/contributing
From now on we'll attempt to keep the repo's CONTRIBUTING.md
documentation in sync with that on the website.
Change-Id: I2c91e6dd5cd7a9b642377878b007d7da3f0ee2ad
The length of the path of #include pragmas can be more than
79-character long. The length of the path of a #include pragma
can be outside of user's control.
The refactoring to the daily tests was missing the dependency on the
'name-artifacts' job, which is necessary for downloading all the gem5
artifacts. This adds it in so the tests run as expected.
Change-Id: I0d71ab147395f41c881f2b24597bc07006e1f9c0
This fixes issue #131 by reverting to the old behavior of performing all
atomics at the system level. To do this the SLC bit needs to be set for
all atomic requests.
Change-Id: I63f4e449be1b02c933832d09700237f8c8026f4c
The refactoring to the daily tests was missing the dependency
on the 'name-artifacts' job, which is necessary for downloading
all the gem5 artifacts. This adds it in so the tests run as
expected.
Change-Id: I0d71ab147395f41c881f2b24597bc07006e1f9c0
This splits up the gem5 library example tests by Suite UID, as right now
running them together uses the runner for a long period of time. It is
important to note that doing this means additional tests from this
directory will need to be manually added, such as the kvm tests.
Change-Id: Ib2a0aca08f9b51b60e9dd0528324372cf2d98c05
The length of the path of the #include pragma can be more than
79-character long.
Change-Id: Id72250c166370c7f456bd1f7d05589a49c14c33d
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
This fixes#131 by reverting to the old behavior of performing all
atomics at the system level. To do this the SLC bit needs to be set for
all atomic requests.
Change-Id: I63f4e449be1b02c933832d09700237f8c8026f4c
In the memory controller, MemCtrl::MemoryPort::recvFunctional, when the
functional request is satisfied by the ctrl-response queue, correctly
make the packet a response.
This change mirrors AbstractMemory::functionalAccess, which uses
Packet::makeResponse() after satisfying the request.
Note:
bool trySatisfyFunctional(..) functions return true or false based on
whether the request was satisfied.
void recvFunctional(..) functions modify the packet to indicate
successful request satisfaction.
This updates the TESTING.md to reflect the current state of the tests in
the gem5 repository and how they interact with the GitHub Actions
infrastructure.
These testing scripts are no longer used since moving to GitHub. The
Nightly (now refered to as "Daily" tests), the Weekly Tests, Compiler
Tests and the CI (Kokoro, pre-commit) tests are run via the GitHub
Actions infrastructure. Their setup is described via Workflow files in
".github/workflows". To run tests locally please consult the
"TESTING.md" file.
These scripts may still be useful to reference and are therefore being
moved into a deprecated state.
Change-Id: Ie75c2f4f1179eb73d0f45ba0b259e8d79aa02ace
This moves the gem5 library example tests into a separate matrix,
so they can run on separate runners
Change-Id: Ie9f51b5bae9e7e424d1c98b545b4cf92b481a2fb
This changes the daily tests to use a matrix in order to run
tests. It also includes forces the cleaning step to run
regardless of success or failure. With this refactoring, now
all builds of gem5 must finish before any tests run, and all
tests download all artifacts from all the build runs.
Change-Id: I16e1bc9acaf619feb85fba53eb6129e7df3fe409
These testing scripts are no longer used since moving to GitHub. The
Nightly (now refered to as "Daily" tests), the Weekly Tests, Compiler
Tests and the CI (Kokoro, pre-commit) tests are run via the GitHub
Actions infrastructure. Their setup is described via Workflow files
in ".github/workflows". To run tests locally please consult the
"TESTING.md" file.
These scripts may still be useful to reference and are therefore being
moved into a deprecated state.
Change-Id: Ie75c2f4f1179eb73d0f45ba0b259e8d79aa02ace
In the memory controller, MemCtrl::MemoryPort::recvFunctional,
when the functional request is satisfied by the ctrl-response queue,
correctly make the packet a response.
This change mirrors AbstractMemory::functionalAccess, which uses
Packet::makeResponse() after satisfying the request.
Change-Id: I47917062d3270915a97eed2c9fade66ba17019eb
This change:
1. Removes the 'Specifying a subset of tests to run' section. This
section is no longer useful since tests are no longer divided up so
neatly by tags as they once were.
2. Adds a section outlining the 'quick', 'long' and 'very-long' tests
and how they may be selected and run.
Change-Id: I61370dd80cc925a15d1a22755faa7d62e810862f
In https://gem5-review.googlesource.com/c/public/gem5/+/52047 inst.pc
was changed from an object to a pointer. It is possible that this
pointer is null (e.g., if there is an interrupt and there is a bubble).
Make sure to check that it's not null before printing.
I believe that other places this pointer is dereferenced without an
explicit null check are safe, but I'm not certain.
Should fix#97
Change-Id: Idbe246cfdb62d4d75416d41b451fb3c076233bbc
When compiling with clang-14 I received the following error:
```
src/base/bitfield.hh:328:1: error: function 'findLsbSetFallback' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration]
```
This function was introduced in PR #76.
This fixes this compiler warning/error by using `[[maybe_unused]]`.
Change-Id: I0b99eab0a9e42ee1687e7a0594a5a7bf9588b422
