Giacomo Travaglini
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d1d90c529c
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configs: Stop using a PTW cache before L2 in Arm configs
This implementation of a walk cache does not allow to skip walks as it
is a simple cache placed in front of the table walker.
It was meant to provide a faster retrieval of page table descriptors
than fetching them from L2 or memory.
This is not needed anymore for Arm as from [1] we implement
partial translation caching in Arm TLBs.
[1]: JIRA: https://gem5.atlassian.net/browse/GEM5-1108
Change-Id: I00d44a4e3961e15602bf4352f2f42ddccf2b746b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54243
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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2021-12-16 09:00:53 +00:00 |
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Giacomo Travaglini
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a2c9213a31
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configs, tests: Replace optparse with argparse
JIRA: https://gem5.atlassian.net/browse/GEM5-543
Change-Id: I997d6a4e45319a74e21bd0d61d4af6118474c849
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44513
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
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2021-04-21 20:42:37 +00:00 |
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Giacomo Travaglini
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47a278c0ad
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configs: RubySimpleSystem and simple ruby_fs.py script
This patch is providing a minimal ruby powered script
for Arm simulations
Change-Id: Ifb2d827362e2d5de5d15c70b200598f9f714f7f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43288
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
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2021-03-25 09:37:13 +00:00 |
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