src/mem/bus.cc:
Fixes to the previous hand merging, and put the snooping back into recvTiming and out of it's own function.
src/mem/bus.hh:
Put snooping back into recvTiming and not in it's own function.
--HG--
extra : convert_revision : fd031b7e6051a5be07ed6926454fde73b1739dc6
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
src/mem/bus.cc:
Hand merged. Needs to be fixed
--HG--
extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
Fix an issue with memory handling writebacks.
src/mem/cache/base_cache.hh:
src/mem/tport.cc:
Only respond if the pkt needs a response.
src/mem/physical.cc:
Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.
--HG--
extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
src/mem/bus.cc:
src/mem/bus.hh:
minor fix and some formatting changes
src/python/m5/objects/Bus.py:
changed bits to bytes
--HG--
extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
For now, responses have priority over requests (may want to revist this).
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Add mechanism for caches to handle failure of the fast path on responses.
--HG--
extra : convert_revision : 01524c727d1bb300cc21bdc989eb862ec8bf0b7a
src/mem/cache/cache_impl.hh:
Make sure to pop the list. Fixes infinite writeback bug.
src/mem/cache/miss/mshr_queue.cc:
Add an assert as sanity check in case .full() stops working again.
--HG--
extra : convert_revision : d847e49a397eeb0b7c5ac060fcfc3eaeac921311
Fix so that blocking for the same reason doesn't fail. I.E. multiple writebacks want to set the blocked flag.
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
Remove threadnum from cache everywhere for now
--HG--
extra : convert_revision : 7890712147655280b4f1439d486feafbd5b18b2b
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again).
2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier.
src/arch/alpha/isa/decoder.isa:
src/mem/cache/cache_impl.hh:
modify arg. order for new calling convention of exitSimLoop.
src/cpu/base.cc:
src/sim/main.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args.
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_exit.hh:
add the periodicity of checkpointing back into the code.
to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop). exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future.
--HG--
extra : convert_revision : c61f4bf05517172edd2c83368fd10bb0f0678029
And small other tweaks to snooping coherence.
src/mem/cache/base_cache.hh:
Make timing response at the time of send.
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
Update probe interface to be bi-directional for functional accesses
src/mem/packet.hh:
Add the function to create an atomic response to a given request
--HG--
extra : convert_revision : 04075a117cf30a7df16e6d3ce485543cc77d4ca6
Still need:
-Handle NACK's on the recieve side
-Distinguish top level caches
-Handle repsonses from caches failing the fast path
-Handle BusError and propogate it
-Fix the invalidate packet associated with snooping in the cache
src/mem/bus.cc:
Make sure to snoop on functional accesses
src/mem/cache/base_cache.cc:
Wait to make a request into a response until it is ready to be issued
src/mem/cache/base_cache.hh:
Support range changes for snoops
Set up snoop responses for cache->cache transfers
src/mem/cache/cache_impl.hh:
Only access the cache if it wasn't satisfied by cache->cache transfer
Handle snoop phases (detect block, then snoop)
Fix functional access to work properly (still need to fix snoop path for functional accesses)
--HG--
extra : convert_revision : 4c25f11d7a996c1f56f4f7b55dde87a344e5fdf8
Working on pulling out the changes in the cache so that it remains working.
src/mem/bus.cc:
Changes for multi-phase snoop
Some code for registering snoop ranges (a version that compiles and runs, but does nothing)
src/mem/bus.hh:
Changes for multi-phase snoop
src/mem/packet.hh:
Flag for multi-phase snoop
src/mem/port.hh:
Status for multi-phase snoop
--HG--
extra : convert_revision : 4c2e5263bba16e3bcf03aabe36ff45ec36de4720
Kinda port DRAM to new memory system. The code is *really* ugly (not my fault) and right now something about the stats it uses
causes a simulator segfault.
src/SConscript:
Add dram.cc to sconscript
src/mem/physical.cc:
src/mem/physical.hh:
Add params struct to physical memory, use params, make latency function be virtual
src/python/m5/objects/PhysicalMemory.py:
Add DRAMMemory python class
--HG--
extra : convert_revision : 5bd9f2e071c62da89e8efa46fa016f342c01535d
src/mem/cache/base_cache.cc:
Add in retry path for blocking with multi-level caches
src/mem/cache/base_cache.hh:
Pull more of the blocking fixes into head
src/mem/packet.hh:
Fix typo
--HG--
extra : convert_revision : d4d149adfa414136ebd2c4789b739bb065710f7a
Nate needs to fix sinic builder stuff
Gabe needs to verify my fixes to decoder.isa
OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset
README:
Fix the swig version in the readme
src/SConscript:
remove sinic until nate fixes the builder crap for it
src/arch/alpha/system.hh:
src/arch/mips/isa/includes.isa:
src/arch/sparc/isa/decoder.isa:
src/base/stats/visit.cc:
src/base/timebuf.hh:
src/dev/ide_disk.cc:
src/dev/sinic.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr_queue.cc:
src/mem/packet.hh:
src/mem/request.hh:
src/sim/builder.hh:
src/sim/system.hh:
fixes for gcc 4.1
--HG--
extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
-Basically removed the ASID from places it is no longer needed due to PageTable
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
Remove asid where it wasn't neccesary anymore due to Page Table
--HG--
extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28
Make PioPort use it
Make Physical memory use it as well
src/SConscript:
Add timing port to sconscript
src/dev/io_device.cc:
src/dev/io_device.hh:
Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory
src/mem/physical.cc:
src/mem/physical.hh:
use a simple timing port stuff instead of rolling our own here
--HG--
extra : convert_revision : e5befbd295a572568cfdca533efb5ed1984c59d1
src/mem/cache/base_cache.cc:
If we still have outstanding requests, need to schedule event again
src/mem/cache/miss/miss_queue.cc:
Need to use block size so overlapping requests match in the MSHR's
src/mem/cache/miss/mshr.cc:
Actually save the address, otherwise we can't match MSHR's
--HG--
extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
