22333 Commits

Author SHA1 Message Date
fb29eaab11 Fix missing include 2025-03-29 14:54:42 +01:00
b2f5575f9c Fix DRAMPower linkage issue with gem5 2025-03-25 13:25:53 +00:00
a5ba2bf60d Fix nlohmann_json include 2025-03-25 14:01:37 +01:00
705f1295c7 Use fetch content in DRAMSys 2025-03-25 12:45:34 +00:00
bebf9d05f2 tests: Update DRAMSys test to use new version 2025-03-25 13:04:14 +01:00
e89a9e22f5 ext,stdlib: Update integration of DRAMSys
The latest version of DRAMSys required several API changes which were
applied in this commit.

Also, the README for the usage of DRAMSys has been updated.

The updated version fixes a bug in DRAMSys that caused some full-system
simulations to loop endlessly.

GitHub Issue: https://github.com/gem5/gem5/issues/1452
2025-03-25 13:03:38 +01:00
43fbdd853f Wallclock time plots 2025-03-21 18:17:12 +01:00
353488837c Prepare dataframe format for Latex plots 2025-03-21 18:17:12 +01:00
3d9533c10c First plotting scripts 2025-03-21 18:17:12 +01:00
da29aa865b First plot script 2025-03-21 18:17:12 +01:00
2212a03ae4 Add simulation script 2025-03-21 18:17:12 +01:00
51de880666 Update configuration 2025-03-21 18:17:12 +01:00
438d997ddb Increase HBM2 memory size to 2 GiB 2025-03-21 18:16:43 +01:00
e423da5256 Add support for shared pim units 2025-03-21 18:15:44 +01:00
e1c6318edb Integrate additional pim-vm library in DRAMSys linking 2025-03-21 18:15:44 +01:00
f28b51fce0 Enable m5ops and change cache line size to 32 2025-03-21 18:15:44 +01:00
7c183df27b First PIM modifications 2025-03-21 18:15:44 +01:00
Bobby R. Bruce
186a913a48 misc: Hotfix v24.1.0.2 (#1964)
This adds #1930 as a hotfix to gem5 v24.1.0
2025-02-12 12:09:26 -08:00
Bobby R. Bruce
7d6d253f6b misc: Update release notes for v24.1.0.2 2025-02-02 01:02:59 -08:00
Bobby R. Bruce
8f2ccca3a3 misc: Update version to v24.1.0.2 2025-02-02 00:56:30 -08:00
Adrià Armejach
dc448c9530 mem-ruby: set RubySystem pointer during TBE alloc (#1930)
Currently the RubySystem pointer is set when set_tbe is performed, which
effectively clears the NetDest objects from the TBE (if any). This is
fine if the TBE has been just allocated before set_tbe is called (no
NetDest info in the TBE). However, the CHI protocol has an action
(RestoreFromHazard) that performs a set_tbe over a TBE that had already
been set, i.e., it already has valid NetDest data.

This patch sets the RubySystem pointer when the TBE is allocated, which
is more natural and follows the style already adopted in the
PerfectCacheMemory class (#1864).

Co-authored-by: Adrià Armejach <adria.armejach@bsc.es>
2025-02-01 23:34:55 -08:00
Bobby R. Bruce
c9625ce9cc v24.1.0.1 Hotfix Release (#1875) 2024-12-19 18:28:44 -08:00
Bobby R. Bruce
ea28fcee5b misc: Update RELEASE-NOTES.md for v24.1.0.1 2024-12-19 18:27:30 -08:00
Bobby R. Bruce
0e4c8487dd misc: Update the gem5 version to v24.1.0.1 2024-12-19 18:24:22 -08:00
Tommaso Marinelli
b5e27f5ed8 configs: Generalize class types in CHI RNF/MN generators (#1851)
Classes CHI_RNF and CHI_MN can be specialized to override base
class/subclass attributes, like it happens in CustomMesh with
router_list (see configs/example/noc_config/2x4.py). To avoid missing
these attributes, it is needed to generalize the class types when
instantiating the objects in the recently added generators.
2024-12-18 21:16:26 -08:00
Melissa Jost
e146f1b2bc misc: Add sphinx stdlib documentation (#335)
This PR adds documentation to the standard library using Sphinx. For
details on how the documentation was generated, refer to
https://gem5.atlassian.net/browse/GEM5-1314. Currently, some modules
like `dramsys` and `mesi_three_level` appear as blank pages. To view the
current state of the documentation locally, run: `cd docs/_build/html;
python3 -m http.server 8000`


---------
Co-authored-by: ivanaamit <ivanamit91@gmail.com>
2024-12-18 21:14:10 -08:00
Marleson Graf
b6c941c9ca mem-ruby: Fix missing RubySystem in PerfectCacheMemory's entries (#1864)
MOESI_CMP_directory protocol crashes with one of the several assertions
in NetDest.cc. It happens because the entry type used to instantiate a
PerfectCacheMemory object in MOESI_CMP_directory-L2cache.sm contains a
NetDest object, so it requires a RubySystem object to be manually set
for it.

Instead of just receiving the block size, change PerfectCacheMemory to
receive a RubySystem object and use it to set the block size and call
ENTRY::setRubySystem if the entries require it.
2024-12-18 21:13:32 -08:00
Marleson Graf
0fe31664f3 mem-ruby: Add missing option in ProtocolInfo (#1865)
After the support for multiple ruby protocols was added, the macros
PROTOCOL_MESI_Two_Level and PROTOCOL_MESI_Three_Level were removed.
These macros are still being used to determine if Load_Linked requests
are sent to the protocol, an information required by the fix that
addresses LL/SC livelock.
Replace the macros with a new option: useSecondaryLoadLinked.
2024-12-18 21:12:57 -08:00
Harshil Patel
63d25922a2 tests: Update pyunit tests references to include 24.1 (#1843) 2024-12-07 00:02:57 -08:00
Vishnu Ramadas
8877516e5b mem-ruby: Fix GPU_VIPER-TCP.sm atomic transitions in TCC WB mode
The transition that happens when TCC acknowledges TCP of an atomic
operation completion does not move the cacheline state from A to I. This
commit fixes the transition and moves the state to I
2024-12-06 23:17:46 -08:00
Vishnu Ramadas
6aa9db28f1 mem-ruby: Fix segfault in pa_performAtomics in GPU_VIPER-TCC.sm
When the cache is performing an atomics and receives data, it performs.
pa_performAtomic. This action peeks into the coreRequest queue to check
the messaage type. This queue, however, is already dequeued in the
transition that precedes the one that contains pa_performAtomic. When
pa_performAtomic is called, the simulation crashes. This commit fixes
the crash by using the TBE entry information instead of peeking when TBE
entry exists, and peeking when it doesn't
2024-12-06 23:17:10 -08:00
Jason Lowe-Power
93b58fbf64 misc: Add GPU info to release notes (#1844)
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Co-authored-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Co-authored-by: Matt Sinclair <mattdsinclair.wisc@gmail.com>
2024-12-06 21:59:24 -08:00
Bobby R. Bruce
ae60062a9e mem-ruby,misc: Fix RNG range (#1842)
This upper range must be `UINT_MAX - 1`. This was previously fixed but
reverted back. Without this the RNG crashes.
2024-12-06 21:58:52 -08:00
Bobby R. Bruce
26ba6dad80 scons: Remove warn as error for v24.1 2024-12-06 19:45:58 -08:00
Erin Le
4559bafaa6 arch-riscv: Remove warning message in senvcfg setMiscReg
Previously, a warning would be printed when the WPRI bits
in the senvcfg register were written to. The other registers
do not print warnings for this, so the warning is being
removed.
2024-12-06 19:38:39 -08:00
Erin Le
e6b931213f arch-riscv: Implement behavior for senvcfg register
This commit adds behavior for writes to the senvcfg register.
It also implements the CBIE, CBCFE, and CBZE bitfields of
senvcfg.
2024-12-06 19:38:24 -08:00
Erin Le
3b62f1f8e4 arch-riscv: Add senvcfg CSR
This commit adds the senvcfg CSR, which fixes the 6.11.3 kernel
crash documented in issue 1674. I have not added a bitfield and
its implementation in isa.cc only uses setMiscRegNoEffect, so
this implementation is likely missing some critical components.
2024-12-06 19:38:14 -08:00
Erin (Jianghua) Le
8f37677c9b misc: v24.1 release notes update (#1840) 2024-12-06 16:13:43 -08:00
Clement Dieperink
2b645ed38c arch-riscv: fix tlb stats in timming mode (#1832)
The previous #484 issue reported a bug where the TLB stats on RISC-V
were incremented twice on misses by calling the `lookup` function twice
with hidden argument set to `false`. The fix is only applied on atomic
mode as the `translation` argument of `doTranslate` will not be
`nullptr` in timing mode.

In that case, if the TLB lookup miss, the `doTranslate` function will
start the walker and then return without doing anything more. Then
later, when the pagetable walker found the corresponding PTE, it will
insert it and call `translateWithTLB`. This function then call `lookup`
again which will hit in any case (and crash if not due to the following
assert), but the hit count is incremented here too. 

This commit fix by setting the `hidden` argument of `lookup` to true.
2024-12-06 11:27:52 -08:00
Bobby R. Bruce
3711bf8a7a base,arch-arm: Add GEM5_NO_OPTIMIZE; use in ARM's vfp.hh (#1834)
GCC and CLANG have different annotations for declaring code should not
be optimized. Adding GEM5_NO_OPTIMZE provides gem5 developers a MACRO
that works in both cases.

This change replaces the GCC pragmas in vfp.hh with GEM5_NO_OPTIMIZE
as this solution didn't work with clang.
2024-12-04 21:36:18 -08:00
Jason Lowe-Power
5672d63ae4 mem-ruby: Fix functional access in MI_example (#1838)
In MI_example, when in MI state the block "Maybe_Stale" as in this
controller may have the most up to date value or it could be in the
network. For MII it is guaranteed that this controller has the most up
to date value because it received a PUTX_NACK.

This fixes one of the daily test failures.
2024-12-04 21:35:46 -08:00
Harshil Patel
a8db1fc683 scons: get protocol info from slicc instead of file parsing 2024-12-04 21:35:14 -08:00
Harshil Patel
02a5ddaeac mem-ruby, scons: Add ProtocolInfo.hh files in build targets
- In the new MultiRuby system, the generated ProtocolInfo header files were not being correctly added to the build targets in SCons.

- As a result, when building gem5 with the --duplicate-sources option, these files were mistakenly deleted by SCons.
This happened because SCons treated them as source files instead of generated build targets.

- This commit ensures that the ProtocolInfo header files are explicitly included in the build targets, preventing their unintended removal and fixing the build issue.
2024-12-04 21:34:54 -08:00
Bobby R. Bruce
dee42f1867 arch-riscv: Remove CPU_SET use for non-linux host (#1835)
For non-Linux systems, we use cpu_set_cpu. CPU_SET is a macro that is
not available for non-Linux systems.

Fixes #1720
2024-12-04 15:48:49 -08:00
2channelkrt
f799d91309 ruby-chi: fix wrong ruby-CHI base class name (#1817)
fix ruby-CHI base class name so it actually runs

previously was combined with PR #1797
2024-12-04 15:47:44 -08:00
Giacomo Travaglini
8a9f61c546 misc: Add CHI section to the RELEASE-NOTES.md (#1833)
Change-Id: I2f01dd9c7a45c5f6baf57e4aad0f171417a6efb1

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2024-12-03 00:47:08 -08:00
Bobby R. Bruce
59ca5600ec misc: Update version info for v24.1 2024-12-02 11:10:28 -08:00
Giacomo Travaglini
c64a807f94 misc: Add ArmISA section to the RELEASE-NOTES.md file (#1822) 2024-12-02 09:38:02 -08:00
Junshi Wang
0a22e63467 arch-arm: Fix bug in VQRSHL.
If shiftAmt is 0, bits raise assert, causing core dump.

Change-Id: Ic4285f51a866ffc017645655e98674ca69a15a40
2024-12-02 08:46:57 -08:00
Erin (Jianghua) Le
1e5021c2e3 tests: modify gem5/learning-gem5 ref file to fix failure (#1795)
The test `ruby_test_test-ALL-x86_64-opt-MatchStdout` is currently
failing because the reference file doesn't match the actual output. This
PR changes the reference file to match.
2024-12-02 08:46:10 -08:00