arch-gcn3: implement instruction s_setreg_b32
Instruction s_setreg_b32 was unimplemented, but is used by hipified rodinia 'srad'. The instruction sets values of hardware internal registers. If the instruction is writing into MODE to control single-precision FP round and denorm modes, a simple warn will be printed; for all other cases (non-MODE hw register or other precisions), panic will happen. Change-Id: Idb1cd5f60548a146bc980f1a27faff30259e74ce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29949 Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
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committed by
Anthony Gutierrez
parent
1836d58b36
commit
fff185993a
@@ -1800,6 +1800,7 @@ namespace Gcn3ISA
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Inst_SOPK__S_SETREG_B32::Inst_SOPK__S_SETREG_B32(InFmt_SOPK *iFmt)
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: Inst_SOPK(iFmt, "s_setreg_b32")
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{
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setFlag(ALU);
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} // Inst_SOPK__S_SETREG_B32
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Inst_SOPK__S_SETREG_B32::~Inst_SOPK__S_SETREG_B32()
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@@ -1813,6 +1814,32 @@ namespace Gcn3ISA
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void
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Inst_SOPK__S_SETREG_B32::execute(GPUDynInstPtr gpuDynInst)
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{
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ScalarRegI16 simm16 = instData.SIMM16;
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ScalarRegU32 hwregId = simm16 & 0x3f;
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ScalarRegU32 offset = (simm16 >> 6) & 31;
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ScalarRegU32 size = ((simm16 >> 11) & 31) + 1;
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ScalarOperandU32 hwreg(gpuDynInst, hwregId);
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ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
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hwreg.read();
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sdst.read();
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// Store value from SDST to part of the hardware register.
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ScalarRegU32 mask = (((1U << size) - 1U) << offset);
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hwreg = ((hwreg.rawData() & ~mask)
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| ((sdst.rawData() << offset) & mask));
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hwreg.write();
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// set MODE register to control the behavior of single precision
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// floating-point numbers: denormal mode or round mode
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if (hwregId==1 && size==2
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&& (offset==4 || offset==0)) {
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warn_once("Be cautious that s_setreg_b32 has no real effect "
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"on FP modes: %s\n", gpuDynInst->disassemble());
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return;
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}
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// panic if not changing MODE of floating-point numbers
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panicUnimplemented();
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}
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