derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cpu: Move execute stats from simple and minor to base

Browse Source 
Created stat group ExecuteCPUStats in BaseCPU and moved stats from the
simple and minor cpu models.

The stats moved from SimpleCPU are dcacheStallCycles,
icacheStallCycles, numCCRegReads, numCCRegWrites, numFpAluAccesses,
numFpRegReads, numFpRegWrites, numIntAluAccesses, numIntRegReads,
numIntRegWrites, numMemRefs, numMiscRegReads, numMiscRegWrites,
numVecAluAccesses, numVecPredRegReads, numVecPredRegWrites,
numVecRegReads, numVecRegWrites.

The stat moved from MinorCPU is numDiscardedOps.

Also, ccRegfileReads, ccRegfileWrites, fpRegfileReads, fpRegfileWrites,
intRegfileReads, intRegfileWrites, miscRegfileReads, miscRegfileWrites,
vecPredRegfileReads, vecPredRegfileWrites, vecRegfileReads,
and vecRegfileWrites are removed from cpu.hh and cpu.cc in O3CPU. The
corresponding stats in BaseCPU::ExecuteCPUStats are used instead.
Changed the getReg, getWritableReg, and setReg functions in the O3 CPU
object to take the thread ID as a parameter. This is because the stats
in base are stored in vectors that are indexed by thread ID.

Change-Id: I801c5ceb4c70b7b281127569f11c6ee98f614b27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67390
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Melissa Jost
2023-01-19 00:25:26 -08:00
committed by Bobby Bruce
parent 8a11b39c41
commit fd2d80baa3
10 changed files with 190 additions and 237 deletions
Download Patch File Download Diff File Expand all files Collapse all files

76
src/cpu/base.cc
View File

@@ -193,8 +193,10 @@ BaseCPU::BaseCPU(const Params &p, bool is_checker)
});
// create a stat group object for each thread on this core
fetchStats.reserve(numThreads);
executeStats.reserve(numThreads);
for (int i = 0; i < numThreads; i++) {
fetchStats.emplace_back(new FetchCPUStats(this, i));
executeStats.emplace_back(new ExecuteCPUStats(this, i));
}
}
@@ -846,4 +848,78 @@ FetchCPUStats::FetchCPUStats(statistics::Group *parent, int thread_id)
}
// means it is incremented in a vector indexing and not directly
BaseCPU::
ExecuteCPUStats::ExecuteCPUStats(statistics::Group *parent, int thread_id)
: statistics::Group(parent, csprintf("executeStats%i", thread_id).c_str()),
ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
"DCache total stall cycles"),
ADD_STAT(numCCRegReads, statistics::units::Count::get(),
"Number of times the CC registers were read"),
ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
"Number of times the CC registers were written"),
ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
"Number of float alu accesses"),
ADD_STAT(numFpRegReads, statistics::units::Count::get(),
"Number of times the floating registers were read"),
ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
"Number of times the floating registers were written"),
ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
"Number of integer alu accesses"),
ADD_STAT(numIntRegReads, statistics::units::Count::get(),
"Number of times the integer registers were read"),
ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
"Number of times the integer registers were written"),
ADD_STAT(numMemRefs, statistics::units::Count::get(),
"Number of memory refs"),
ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
"Number of times the Misc registers were read"),
ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
"Number of times the Misc registers were written"),
ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
"Number of vector alu accesses"),
ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
"Number of times the predicate registers were read"),
ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(),
"Number of times the predicate registers were written"),
ADD_STAT(numVecRegReads, statistics::units::Count::get(),
"Number of times the vector registers were read"),
ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
"Number of times the vector registers were written"),
ADD_STAT(numDiscardedOps, statistics::units::Count::get(),
"Number of ops (including micro ops) which were discarded before "
"commit")
{
dcacheStallCycles
.prereq(dcacheStallCycles);
numCCRegReads
.prereq(numCCRegReads)
.flags(statistics::nozero);
numCCRegWrites
.prereq(numCCRegWrites)
.flags(statistics::nozero);
numFpAluAccesses
.prereq(numFpAluAccesses);
numFpRegReads
.prereq(numFpRegReads);
numIntAluAccesses
.prereq(numIntAluAccesses);
numIntRegReads
.prereq(numIntRegReads);
numIntRegWrites
.prereq(numIntRegWrites);
numMiscRegReads
.prereq(numMiscRegReads);
numMiscRegWrites
.prereq(numMiscRegWrites);
numVecPredRegReads
.prereq(numVecPredRegReads);
numVecPredRegWrites
.prereq(numVecPredRegWrites);
numVecRegReads
.prereq(numVecRegReads);
numVecRegWrites
.prereq(numVecRegWrites);
}
} // namespace gem5

48
src/cpu/base.hh
View File

@@ -691,7 +691,55 @@ class BaseCPU : public ClockedObject
};
struct ExecuteCPUStats: public statistics::Group
{
ExecuteCPUStats(statistics::Group *parent, int thread_id);
/* Number of cycles stalled for D-cache responses */
statistics::Scalar dcacheStallCycles;
/* Number of condition code register file accesses */
statistics::Scalar numCCRegReads;
statistics::Scalar numCCRegWrites;
/* number of float alu accesses */
statistics::Scalar numFpAluAccesses;
/* Number of float register file accesses */
statistics::Scalar numFpRegReads;
statistics::Scalar numFpRegWrites;
/* Number of integer alu accesses */
statistics::Scalar numIntAluAccesses;
/* Number of integer register file accesses */
statistics::Scalar numIntRegReads;
statistics::Scalar numIntRegWrites;
/* number of simulated memory references */
statistics::Scalar numMemRefs;
/* Number of misc register file accesses */
statistics::Scalar numMiscRegReads;
statistics::Scalar numMiscRegWrites;
/* Number of vector alu accesses */
statistics::Scalar numVecAluAccesses;
/* Number of predicate register file accesses */
mutable statistics::Scalar numVecPredRegReads;
statistics::Scalar numVecPredRegWrites;
/* Number of vector register file accesses */
mutable statistics::Scalar numVecRegReads;
statistics::Scalar numVecRegWrites;
/* Number of ops discarded before committing */
statistics::Scalar numDiscardedOps;
};
std::vector<std::unique_ptr<FetchCPUStats>> fetchStats;
std::vector<std::unique_ptr<ExecuteCPUStats>> executeStats;
};
} // namespace gem5

2
src/cpu/minor/execute.cc
View File

@@ -1368,7 +1368,7 @@ Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard,
*inst, ex_info.streamSeqNum);
if (fault == NoFault)
cpu.stats.numDiscardedOps++;
cpu.executeStats[thread_id]->numDiscardedOps++;
}
/* Mark the mem inst as being in the LSQ */

3
src/cpu/minor/stats.cc
View File

@@ -49,9 +49,6 @@ MinorStats::MinorStats(BaseCPU *base_cpu)
"Number of instructions committed"),
ADD_STAT(numOps, statistics::units::Count::get(),
"Number of ops (including micro ops) committed"),
ADD_STAT(numDiscardedOps, statistics::units::Count::get(),
"Number of ops (including micro ops) which were discarded before "
"commit"),
ADD_STAT(quiesceCycles, statistics::units::Cycle::get(),
"Total number of cycles that CPU has spent quiesced or waiting "
"for an interrupt"),

3
src/cpu/minor/stats.hh
View File

@@ -65,9 +65,6 @@ struct MinorStats : public statistics::Group
/** Number of simulated insts and microops */
statistics::Scalar numOps;
/** Number of ops discarded before committing */
statistics::Scalar numDiscardedOps;
/** Number of cycles in quiescent state */
statistics::Scalar quiesceCycles;

120
src/cpu/o3/cpu.cc
View File

@@ -344,31 +344,7 @@ CPU::CPUStats::CPUStats(CPU *cpu)
"IPC: Instructions Per Cycle"),
ADD_STAT(totalIpc, statistics::units::Rate<
statistics::units::Count, statistics::units::Cycle>::get(),
"IPC: Total IPC of All Threads"),
ADD_STAT(intRegfileReads, statistics::units::Count::get(),
"Number of integer regfile reads"),
ADD_STAT(intRegfileWrites, statistics::units::Count::get(),
"Number of integer regfile writes"),
ADD_STAT(fpRegfileReads, statistics::units::Count::get(),
"Number of floating regfile reads"),
ADD_STAT(fpRegfileWrites, statistics::units::Count::get(),
"Number of floating regfile writes"),
ADD_STAT(vecRegfileReads, statistics::units::Count::get(),
"number of vector regfile reads"),
ADD_STAT(vecRegfileWrites, statistics::units::Count::get(),
"number of vector regfile writes"),
ADD_STAT(vecPredRegfileReads, statistics::units::Count::get(),
"number of predicate regfile reads"),
ADD_STAT(vecPredRegfileWrites, statistics::units::Count::get(),
"number of predicate regfile writes"),
ADD_STAT(ccRegfileReads, statistics::units::Count::get(),
"number of cc regfile reads"),
ADD_STAT(ccRegfileWrites, statistics::units::Count::get(),
"number of cc regfile writes"),
ADD_STAT(miscRegfileReads, statistics::units::Count::get(),
"number of misc regfile reads"),
ADD_STAT(miscRegfileWrites, statistics::units::Count::get(),
"number of misc regfile writes")
"IPC: Total IPC of All Threads")
{
// Register any of the O3CPU's stats here.
timesIdled
@@ -407,42 +383,6 @@ CPU::CPUStats::CPUStats(CPU *cpu)
totalIpc
.precision(6);
totalIpc = sum(committedInsts) / cpu->baseStats.numCycles;
intRegfileReads
.prereq(intRegfileReads);
intRegfileWrites
.prereq(intRegfileWrites);
fpRegfileReads
.prereq(fpRegfileReads);
fpRegfileWrites
.prereq(fpRegfileWrites);
vecRegfileReads
.prereq(vecRegfileReads);
vecRegfileWrites
.prereq(vecRegfileWrites);
vecPredRegfileReads
.prereq(vecPredRegfileReads);
vecPredRegfileWrites
.prereq(vecPredRegfileWrites);
ccRegfileReads
.prereq(ccRegfileReads);
ccRegfileWrites
.prereq(ccRegfileWrites);
miscRegfileReads
.prereq(miscRegfileReads);
miscRegfileWrites
.prereq(miscRegfileWrites);
}
void
@@ -1019,7 +959,7 @@ CPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
RegVal
CPU::readMiscReg(int misc_reg, ThreadID tid)
{
cpuStats.miscRegfileReads++;
executeStats[tid]->numMiscRegReads++;
return isa[tid]->readMiscReg(misc_reg);
}
@@ -1032,29 +972,29 @@ CPU::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
void
CPU::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
{
cpuStats.miscRegfileWrites++;
executeStats[tid]->numMiscRegWrites++;
isa[tid]->setMiscReg(misc_reg, val);
}
RegVal
CPU::getReg(PhysRegIdPtr phys_reg)
CPU::getReg(PhysRegIdPtr phys_reg, ThreadID tid)
{
switch (phys_reg->classValue()) {
case IntRegClass:
cpuStats.intRegfileReads++;
executeStats[tid]->numIntRegReads++;
break;
case FloatRegClass:
cpuStats.fpRegfileReads++;
executeStats[tid]->numFpRegReads++;
break;
case CCRegClass:
cpuStats.ccRegfileReads++;
executeStats[tid]->numCCRegReads++;
break;
case VecRegClass:
case VecElemClass:
cpuStats.vecRegfileReads++;
executeStats[tid]->numVecRegReads++;
break;
case VecPredRegClass:
cpuStats.vecPredRegfileReads++;
executeStats[tid]->numVecPredRegReads++;
break;
default:
break;
@@ -1063,24 +1003,24 @@ CPU::getReg(PhysRegIdPtr phys_reg)
}
void
CPU::getReg(PhysRegIdPtr phys_reg, void *val)
CPU::getReg(PhysRegIdPtr phys_reg, void *val, ThreadID tid)
{
switch (phys_reg->classValue()) {
case IntRegClass:
cpuStats.intRegfileReads++;
executeStats[tid]->numIntRegReads++;
break;
case FloatRegClass:
cpuStats.fpRegfileReads++;
executeStats[tid]->numFpRegReads++;
break;
case CCRegClass:
cpuStats.ccRegfileReads++;
executeStats[tid]->numCCRegReads++;
break;
case VecRegClass:
case VecElemClass:
cpuStats.vecRegfileReads++;
executeStats[tid]->numVecRegReads++;
break;
case VecPredRegClass:
cpuStats.vecPredRegfileReads++;
executeStats[tid]->numVecPredRegReads++;
break;
default:
break;
@@ -1089,14 +1029,14 @@ CPU::getReg(PhysRegIdPtr phys_reg, void *val)
}
void *
CPU::getWritableReg(PhysRegIdPtr phys_reg)
CPU::getWritableReg(PhysRegIdPtr phys_reg, ThreadID tid)
{
switch (phys_reg->classValue()) {
case VecRegClass:
cpuStats.vecRegfileReads++;
executeStats[tid]->numVecRegReads++;
break;
case VecPredRegClass:
cpuStats.vecPredRegfileReads++;
executeStats[tid]->numVecPredRegReads++;
break;
default:
break;
@@ -1105,24 +1045,24 @@ CPU::getWritableReg(PhysRegIdPtr phys_reg)
}
void
CPU::setReg(PhysRegIdPtr phys_reg, RegVal val)
CPU::setReg(PhysRegIdPtr phys_reg, RegVal val, ThreadID tid)
{
switch (phys_reg->classValue()) {
case IntRegClass:
cpuStats.intRegfileWrites++;
executeStats[tid]->numIntRegWrites++;
break;
case FloatRegClass:
cpuStats.fpRegfileWrites++;
executeStats[tid]->numFpRegWrites++;
break;
case CCRegClass:
cpuStats.ccRegfileWrites++;
executeStats[tid]->numCCRegWrites++;
break;
case VecRegClass:
case VecElemClass:
cpuStats.vecRegfileWrites++;
executeStats[tid]->numVecRegWrites++;
break;
case VecPredRegClass:
cpuStats.vecPredRegfileWrites++;
executeStats[tid]->numVecPredRegWrites++;
break;
default:
break;
@@ -1131,24 +1071,24 @@ CPU::setReg(PhysRegIdPtr phys_reg, RegVal val)
}
void
CPU::setReg(PhysRegIdPtr phys_reg, const void *val)
CPU::setReg(PhysRegIdPtr phys_reg, const void *val, ThreadID tid)
{
switch (phys_reg->classValue()) {
case IntRegClass:
cpuStats.intRegfileWrites++;
executeStats[tid]->numIntRegWrites++;
break;
case FloatRegClass:
cpuStats.fpRegfileWrites++;
executeStats[tid]->numFpRegWrites++;
break;
case CCRegClass:
cpuStats.ccRegfileWrites++;
executeStats[tid]->numCCRegWrites++;
break;
case VecRegClass:
case VecElemClass:
cpuStats.vecRegfileWrites++;
executeStats[tid]->numVecRegWrites++;
break;
case VecPredRegClass:
cpuStats.vecPredRegfileWrites++;
executeStats[tid]->numVecPredRegWrites++;
break;
default:
break;

28
src/cpu/o3/cpu.hh
View File

@@ -310,12 +310,12 @@ class CPU : public BaseCPU
*/
void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
RegVal getReg(PhysRegIdPtr phys_reg);
void getReg(PhysRegIdPtr phys_reg, void *val);
void *getWritableReg(PhysRegIdPtr phys_reg);
RegVal getReg(PhysRegIdPtr phys_reg, ThreadID tid);
void getReg(PhysRegIdPtr phys_reg, void *val, ThreadID tid);
void *getWritableReg(PhysRegIdPtr phys_reg, ThreadID tid);
void setReg(PhysRegIdPtr phys_reg, RegVal val);
void setReg(PhysRegIdPtr phys_reg, const void *val);
void setReg(PhysRegIdPtr phys_reg, RegVal val, ThreadID tid);
void setReg(PhysRegIdPtr phys_reg, const void *val, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
@@ -595,24 +595,6 @@ class CPU : public BaseCPU
/** Stat for the total IPC. */
statistics::Formula totalIpc;
//number of integer register file accesses
statistics::Scalar intRegfileReads;
statistics::Scalar intRegfileWrites;
//number of float register file accesses
statistics::Scalar fpRegfileReads;
statistics::Scalar fpRegfileWrites;
//number of vector register file accesses
mutable statistics::Scalar vecRegfileReads;
statistics::Scalar vecRegfileWrites;
//number of predicate register file accesses
mutable statistics::Scalar vecPredRegfileReads;
statistics::Scalar vecPredRegfileWrites;
//number of CC register file accesses
statistics::Scalar ccRegfileReads;
statistics::Scalar ccRegfileWrites;
//number of misc
statistics::Scalar miscRegfileReads;
statistics::Scalar miscRegfileWrites;
} cpuStats;
public:

14
src/cpu/o3/dyn_inst.hh
View File

@@ -1086,10 +1086,10 @@ class DynInst : public ExecContext, public RefCounted
if (bytes == sizeof(RegVal)) {
setRegOperand(staticInst.get(), idx,
cpu->getReg(prev_phys_reg));
cpu->getReg(prev_phys_reg, threadNumber));
} else {
uint8_t val[original_dest_reg.regClass().regBytes()];
cpu->getReg(prev_phys_reg, val);
cpu->getReg(prev_phys_reg, val, threadNumber);
setRegOperand(staticInst.get(), idx, val);
}
}
@@ -1116,7 +1116,7 @@ class DynInst : public ExecContext, public RefCounted
const PhysRegIdPtr reg = renamedSrcIdx(idx);
if (reg->is(InvalidRegClass))
return 0;
return cpu->getReg(reg);
return cpu->getReg(reg, threadNumber);
}
void
@@ -1125,13 +1125,13 @@ class DynInst : public ExecContext, public RefCounted
const PhysRegIdPtr reg = renamedSrcIdx(idx);
if (reg->is(InvalidRegClass))
return;
cpu->getReg(reg, val);
cpu->getReg(reg, val, threadNumber);
}
void *
getWritableRegOperand(const StaticInst *si, int idx) override
{
return cpu->getWritableReg(renamedDestIdx(idx));
return cpu->getWritableReg(renamedDestIdx(idx), threadNumber);
}
/** @todo: Make results into arrays so they can handle multiple dest
@@ -1143,7 +1143,7 @@ class DynInst : public ExecContext, public RefCounted
const PhysRegIdPtr reg = renamedDestIdx(idx);
if (reg->is(InvalidRegClass))
return;
cpu->setReg(reg, val);
cpu->setReg(reg, val, threadNumber);
setResult(reg->regClass(), val);
}
@@ -1153,7 +1153,7 @@ class DynInst : public ExecContext, public RefCounted
const PhysRegIdPtr reg = renamedDestIdx(idx);
if (reg->is(InvalidRegClass))
return;
cpu->setReg(reg, val);
cpu->setReg(reg, val, threadNumber);
setResult(reg->regClass(), val);
}
};

8
src/cpu/simple/base.cc
View File

@@ -388,7 +388,7 @@ BaseSimpleCPU::postExecute()
Addr instAddr = threadContexts[curThread]->pcState().instAddr();
if (curStaticInst->isMemRef()) {
t_info.execContextStats.numMemRefs++;
executeStats[t_info.thread->threadId()]->numMemRefs++;
}
if (curStaticInst->isLoad()) {
@@ -402,19 +402,19 @@ BaseSimpleCPU::postExecute()
/* Power model statistics */
//integer alu accesses
if (curStaticInst->isInteger()){
t_info.execContextStats.numIntAluAccesses++;
executeStats[t_info.thread->threadId()]->numIntAluAccesses++;
t_info.execContextStats.numIntInsts++;
}
//float alu accesses
if (curStaticInst->isFloating()){
t_info.execContextStats.numFpAluAccesses++;
executeStats[t_info.thread->threadId()]->numFpAluAccesses++;
t_info.execContextStats.numFpInsts++;
}
//vector alu accesses
if (curStaticInst->isVector()){
t_info.execContextStats.numVecAluAccesses++;
executeStats[t_info.thread->threadId()]->numVecAluAccesses++;
t_info.execContextStats.numVecInsts++;
}

125
src/cpu/simple/exec_context.hh
View File

@@ -90,12 +90,6 @@ class SimpleExecContext : public ExecContext
"Number of instructions committed"),
ADD_STAT(numOps, statistics::units::Count::get(),
"Number of ops (including micro ops) committed"),
ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
"Number of integer alu accesses"),
ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
"Number of float alu accesses"),
ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
"Number of vector alu accesses"),
ADD_STAT(numMatAluAccesses, statistics::units::Count::get(),
"Number of matrix alu accesses"),
ADD_STAT(numCallsReturns, statistics::units::Count::get(),
@@ -110,32 +104,6 @@ class SimpleExecContext : public ExecContext
"Number of vector instructions"),
ADD_STAT(numMatInsts, statistics::units::Count::get(),
"Number of matrix instructions"),
ADD_STAT(numIntRegReads, statistics::units::Count::get(),
"Number of times the integer registers were read"),
ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
"Number of times the integer registers were written"),
ADD_STAT(numFpRegReads, statistics::units::Count::get(),
"Number of times the floating registers were read"),
ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
"Number of times the floating registers were written"),
ADD_STAT(numVecRegReads, statistics::units::Count::get(),
"Number of times the vector registers were read"),
ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
"Number of times the vector registers were written"),
ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
"Number of times the predicate registers were read"),
ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(),
"Number of times the predicate registers were written"),
ADD_STAT(numCCRegReads, statistics::units::Count::get(),
"Number of times the CC registers were read"),
ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
"Number of times the CC registers were written"),
ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
"Number of times the Misc registers were read"),
ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
"Number of times the Misc registers were written"),
ADD_STAT(numMemRefs, statistics::units::Count::get(),
"Number of memory refs"),
ADD_STAT(numLoadInsts, statistics::units::Count::get(),
"Number of load instructions"),
ADD_STAT(numStoreInsts, statistics::units::Count::get(),
@@ -148,10 +116,6 @@ class SimpleExecContext : public ExecContext
"Percentage of non-idle cycles"),
ADD_STAT(idleFraction, statistics::units::Ratio::get(),
"Percentage of idle cycles"),
ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
"ICache total stall cycles"),
ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
"DCache total stall cycles"),
ADD_STAT(numPredictedBranches, statistics::units::Count::get(),
"Number of branches predicted as taken"),
ADD_STAT(numBranchMispred, statistics::units::Count::get(),
@@ -159,36 +123,25 @@ class SimpleExecContext : public ExecContext
ADD_STAT(statExecutedInstType, statistics::units::Count::get(),
"Class of executed instruction."),
numRegReads{
&numIntRegReads,
&numFpRegReads,
&numVecRegReads,
&numVecRegReads,
&numVecPredRegReads,
&numMatRegReads,
&numCCRegReads
&(cpu->executeStats[thread->threadId()]->numIntRegReads),
&(cpu->executeStats[thread->threadId()]->numFpRegReads),
&(cpu->executeStats[thread->threadId()]->numVecRegReads),
&(cpu->executeStats[thread->threadId()]->numVecRegReads),
&(cpu->executeStats[thread->threadId()]->numVecPredRegReads),
&(cpu->executeStats[thread->threadId()]->numCCRegReads),
&numMatRegReads
},
numRegWrites{
&numIntRegWrites,
&numFpRegWrites,
&numVecRegWrites,
&numVecRegWrites,
&numVecPredRegWrites,
&numMatRegWrites,
&numCCRegWrites
&(cpu->executeStats[thread->threadId()]->numIntRegWrites),
&(cpu->executeStats[thread->threadId()]->numFpRegWrites),
&(cpu->executeStats[thread->threadId()]->numVecRegWrites),
&(cpu->executeStats[thread->threadId()]->numVecRegWrites),
&(cpu->executeStats[thread->threadId()]
->numVecPredRegWrites),
&(cpu->executeStats[thread->threadId()]->numCCRegWrites),
&numMatRegWrites
}
{
numCCRegReads
.flags(statistics::nozero);
numCCRegWrites
.flags(statistics::nozero);
icacheStallCycles
.prereq(icacheStallCycles);
dcacheStallCycles
.prereq(dcacheStallCycles);
statExecutedInstType
.init(enums::Num_OpClass)
.flags(statistics::total | statistics::pdf | statistics::dist);
@@ -212,15 +165,6 @@ class SimpleExecContext : public ExecContext
statistics::Scalar numInsts;
statistics::Scalar numOps;
// Number of integer alu accesses
statistics::Scalar numIntAluAccesses;
// Number of float alu accesses
statistics::Scalar numFpAluAccesses;
// Number of vector alu accesses
statistics::Scalar numVecAluAccesses;
// Number of matrix alu accesses
statistics::Scalar numMatAluAccesses;
@@ -242,36 +186,11 @@ class SimpleExecContext : public ExecContext
// Number of matrix instructions
statistics::Scalar numMatInsts;
// Number of integer register file accesses
statistics::Scalar numIntRegReads;
statistics::Scalar numIntRegWrites;
// Number of float register file accesses
statistics::Scalar numFpRegReads;
statistics::Scalar numFpRegWrites;
// Number of vector register file accesses
mutable statistics::Scalar numVecRegReads;
statistics::Scalar numVecRegWrites;
// Number of predicate register file accesses
mutable statistics::Scalar numVecPredRegReads;
statistics::Scalar numVecPredRegWrites;
// Number of matrix register file accesses
mutable statistics::Scalar numMatRegReads;
statistics::Scalar numMatRegWrites;
// Number of condition code register file accesses
statistics::Scalar numCCRegReads;
statistics::Scalar numCCRegWrites;
// Number of misc register file accesses
statistics::Scalar numMiscRegReads;
statistics::Scalar numMiscRegWrites;
// Number of simulated memory references
statistics::Scalar numMemRefs;
statistics::Scalar numLoadInsts;
statistics::Scalar numStoreInsts;
@@ -285,12 +204,6 @@ class SimpleExecContext : public ExecContext
statistics::Average notIdleFraction;
statistics::Formula idleFraction;
// Number of cycles stalled for I-cache responses
statistics::Scalar icacheStallCycles;
// Number of cycles stalled for D-cache responses
statistics::Scalar dcacheStallCycles;
/// @{
/// Number of branches predicted as taken
statistics::Scalar numPredictedBranches;
@@ -361,7 +274,7 @@ class SimpleExecContext : public ExecContext
RegVal
readMiscRegOperand(const StaticInst *si, int idx) override
{
execContextStats.numMiscRegReads++;
cpu->executeStats[thread->threadId()]->numMiscRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.is(MiscRegClass));
return thread->readMiscReg(reg.index());
@@ -370,7 +283,7 @@ class SimpleExecContext : public ExecContext
void
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
execContextStats.numMiscRegWrites++;
cpu->executeStats[thread->threadId()]->numMiscRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(MiscRegClass));
thread->setMiscReg(reg.index(), val);
@@ -383,7 +296,7 @@ class SimpleExecContext : public ExecContext
RegVal
readMiscReg(int misc_reg) override
{
execContextStats.numMiscRegReads++;
cpu->executeStats[thread->threadId()]->numMiscRegReads++;
return thread->readMiscReg(misc_reg);
}
@@ -394,7 +307,7 @@ class SimpleExecContext : public ExecContext
void
setMiscReg(int misc_reg, RegVal val) override
{
execContextStats.numMiscRegWrites++;
cpu->executeStats[thread->threadId()]->numMiscRegWrites++;
thread->setMiscReg(misc_reg, val);
}