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misc: Replace M5_VAR_USED with GEM5_VAR_USED.

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Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Gabe Black
2021-05-08 20:23:10 -07:00
parent e55ae090b3
commit fb3befcc6d
69 changed files with 133 additions and 132 deletions
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4
src/mem/cache/base.cc vendored
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@@ -896,7 +896,7 @@ BaseCache::updateCompressionData(CacheBlk *&blk, const uint64_t* data,
// Get previous compressed size
CompressionBlk* compression_blk = static_cast<CompressionBlk*>(blk);
M5_VAR_USED const std::size_t prev_size = compression_blk->getSizeBits();
GEM5_VAR_USED const std::size_t prev_size = compression_blk->getSizeBits();
// If compressed size didn't change enough to modify its co-allocatability
// there is nothing to do. Otherwise we may be facing a data expansion
@@ -2418,7 +2418,7 @@ BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
if (cache->system->bypassCaches()) {
// Just forward the packet if caches are disabled.
// @todo This should really enqueue the packet rather
M5_VAR_USED bool success = cache->memSidePort.sendTimingReq(pkt);
GEM5_VAR_USED bool success = cache->memSidePort.sendTimingReq(pkt);
assert(success);
return true;
} else if (tryTiming(pkt)) {

6
src/mem/cache/cache.cc vendored
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@@ -449,7 +449,7 @@ Cache::recvTimingReq(PacketPtr pkt)
// this express snoop travels towards the memory, and at
// every crossbar it is snooped upwards thus reaching
// every cache in the system
M5_VAR_USED bool success = memSidePort.sendTimingReq(snoop_pkt);
GEM5_VAR_USED bool success = memSidePort.sendTimingReq(snoop_pkt);
// express snoops always succeed
assert(success);
@@ -992,7 +992,7 @@ Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing,
// responds in atomic mode, so remember a few things about the
// original packet up front
bool invalidate = pkt->isInvalidate();
M5_VAR_USED bool needs_writable = pkt->needsWritable();
GEM5_VAR_USED bool needs_writable = pkt->needsWritable();
// at the moment we could get an uncacheable write which does not
// have the invalidate flag, and we need a suitable way of dealing
@@ -1394,7 +1394,7 @@ Cache::sendMSHRQueuePacket(MSHR* mshr)
// prefetchSquash first may result in the MSHR being
// prematurely deallocated.
if (snoop_pkt.cacheResponding()) {
M5_VAR_USED auto r = outstandingSnoop.insert(snoop_pkt.req);
GEM5_VAR_USED auto r = outstandingSnoop.insert(snoop_pkt.req);
assert(r.second);
// if we are getting a snoop response with no sharers it

2
src/mem/cache/compressors/frequent_values.cc vendored
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@@ -141,7 +141,7 @@ FrequentValues::decompress(const CompressionData* comp_data, uint64_t* data)
// its corresponding value, in order to make life easier we
// search for the value and verify that the stored code
// matches the table's
M5_VAR_USED const Encoder::Code code =
GEM5_VAR_USED const Encoder::Code code =
encoder.encode(comp_chunk.value);
// Either the value will be found and the codes match, or the

2
src/mem/cache/tags/fa_lru.cc vendored
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@@ -110,7 +110,7 @@ void
FALRU::invalidate(CacheBlk *blk)
{
// Erase block entry reference in the hash table
M5_VAR_USED auto num_erased =
GEM5_VAR_USED auto num_erased =
tagHash.erase(std::make_pair(blk->getTag(), blk->isSecure()));
// Sanity check; only one block reference should be erased

4
src/mem/coherent_xbar.cc
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@@ -638,7 +638,7 @@ CoherentXBar::recvTimingSnoopResp(PacketPtr pkt, PortID cpu_side_port_id)
*memSidePorts[dest_port_id]);
}
M5_VAR_USED bool success =
GEM5_VAR_USED bool success =
memSidePorts[dest_port_id]->sendTimingSnoopResp(pkt);
pktCount[cpu_side_port_id][dest_port_id]++;
pktSize[cpu_side_port_id][dest_port_id] += pkt_size;
@@ -858,7 +858,7 @@ CoherentXBar::recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id,
// if this is the destination of the operation, the xbar
// sends the responce to the cache clean operation only
// after having encountered the cache clean request
M5_VAR_USED auto ret = outstandingCMO.emplace(pkt->id, nullptr);
GEM5_VAR_USED auto ret = outstandingCMO.emplace(pkt->id, nullptr);
// in atomic mode we know that the WriteClean packet should
// precede the clean request
assert(ret.second);

2
src/mem/dramsim2_wrapper.cc
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@@ -169,7 +169,7 @@ DRAMSim2Wrapper::canAccept() const
void
DRAMSim2Wrapper::enqueue(bool is_write, uint64_t addr)
{
M5_VAR_USED bool success = dramsim->addTransaction(is_write, addr);
GEM5_VAR_USED bool success = dramsim->addTransaction(is_write, addr);
assert(success);
}

2
src/mem/dramsim3_wrapper.cc
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@@ -123,7 +123,7 @@ DRAMsim3Wrapper::canAccept(uint64_t addr, bool is_write) const
void
DRAMsim3Wrapper::enqueue(uint64_t addr, bool is_write)
{
M5_VAR_USED bool success = dramsim->AddTransaction(addr, is_write);
GEM5_VAR_USED bool success = dramsim->AddTransaction(addr, is_write);
assert(success);
}

2
src/mem/external_slave.cc
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@@ -97,7 +97,7 @@ Tick
StubSlavePort::recvAtomic(PacketPtr packet)
{
if (Debug::ExternalPort) {
M5_VAR_USED unsigned int size = packet->getSize();
GEM5_VAR_USED unsigned int size = packet->getSize();
DPRINTF(ExternalPort, "StubSlavePort: recvAtomic a: 0x%x size: %d"
" data: ...\n", packet->getAddr(), size);

2
src/mem/page_table.cc
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@@ -78,7 +78,7 @@ EmulationPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
new_vaddr, size);
while (size > 0) {
M5_VAR_USED auto new_it = pTable.find(new_vaddr);
GEM5_VAR_USED auto new_it = pTable.find(new_vaddr);
auto old_it = pTable.find(vaddr);
assert(old_it != pTable.end() && new_it == pTable.end());

2
src/mem/ruby/network/garnet/GarnetNetwork.cc
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@@ -128,7 +128,7 @@ GarnetNetwork::init()
for (std::vector<Router*>::const_iterator i= m_routers.begin();
i != m_routers.end(); ++i) {
Router* router = safe_cast<Router*>(*i);
M5_VAR_USED int router_id =
GEM5_VAR_USED int router_id =
fault_model->declare_router(router->get_num_inports(),
router->get_num_outports(),
router->get_vc_per_vnet(),

2
src/mem/ruby/network/garnet/RoutingUnit.cc
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@@ -201,7 +201,7 @@ RoutingUnit::outportComputeXY(RouteInfo route,
{
PortDirection outport_dirn = "Unknown";
M5_VAR_USED int num_rows = m_router->get_net_ptr()->getNumRows();
GEM5_VAR_USED int num_rows = m_router->get_net_ptr()->getNumRows();
int num_cols = m_router->get_net_ptr()->getNumCols();
assert(num_rows > 0 && num_cols > 0);

4
src/mem/ruby/structures/CacheMemory.cc
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@@ -408,8 +408,8 @@ void
CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
{
uint64_t warmedUpBlocks = 0;
M5_VAR_USED uint64_t totalBlocks = (uint64_t)m_cache_num_sets *
(uint64_t)m_cache_assoc;
GEM5_VAR_USED uint64_t totalBlocks = (uint64_t)m_cache_num_sets *
(uint64_t)m_cache_assoc;
for (int i = 0; i < m_cache_num_sets; i++) {
for (int j = 0; j < m_cache_assoc; j++) {

2
src/mem/ruby/structures/PerfectCacheMemory.hh
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@@ -150,7 +150,7 @@ template<class ENTRY>
inline void
PerfectCacheMemory<ENTRY>::deallocate(Addr address)
{
M5_VAR_USED auto num_erased = m_map.erase(makeLineAddress(address));
GEM5_VAR_USED auto num_erased = m_map.erase(makeLineAddress(address));
assert(num_erased == 1);
}

2
src/mem/ruby/system/GPUCoalescer.cc
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@@ -532,7 +532,7 @@ GPUCoalescer::hitCallback(CoalescedRequest* crequest,
{
PacketPtr pkt = crequest->getFirstPkt();
Addr request_address = pkt->getAddr();
M5_VAR_USED Addr request_line_address = makeLineAddress(request_address);
GEM5_VAR_USED Addr request_line_address = makeLineAddress(request_address);
RubyRequestType type = crequest->getRubyType();

6
src/mem/ruby/system/RubyPort.cc
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@@ -206,7 +206,7 @@ RubyPort::PioResponsePort::recvTimingReq(PacketPtr pkt)
if (it->contains(pkt->getAddr())) {
// generally it is not safe to assume success here as
// the port could be blocked
M5_VAR_USED bool success =
GEM5_VAR_USED bool success =
ruby_port->request_ports[i]->sendTimingReq(pkt);
assert(success);
return true;
@@ -373,7 +373,7 @@ RubyPort::MemResponsePort::recvFunctional(PacketPtr pkt)
{
DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
M5_VAR_USED RubyPort *rp = static_cast<RubyPort *>(&owner);
GEM5_VAR_USED RubyPort *rp = static_cast<RubyPort *>(&owner);
RubySystem *rs = rp->m_ruby_system;
// Check for pio requests and directly send them to the dedicated
@@ -600,7 +600,7 @@ RubyPort::PioResponsePort::getAddrRanges() const
ranges.splice(ranges.begin(),
ruby_port->request_ports[i]->getAddrRanges());
}
for (M5_VAR_USED const auto &r : ranges)
for (GEM5_VAR_USED const auto &r : ranges)
DPRINTF(RubyPort, "%s\n", r.to_string());
return ranges;
}

2
src/mem/ruby/system/RubySystem.cc
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@@ -691,7 +691,7 @@ RubySystem::functionalWrite(PacketPtr pkt)
DPRINTF(RubySystem, "Functional Write request for %#x\n", addr);
M5_VAR_USED uint32_t num_functional_writes = 0;
GEM5_VAR_USED uint32_t num_functional_writes = 0;
// Only send functional requests within the same network.
assert(requestorToNetwork.count(pkt->requestorId()));

2
src/mem/slicc/ast/PeekStatementAST.py
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@@ -61,7 +61,7 @@ class PeekStatementAST(StatementAST):
code('''
{
// Declare message
M5_VAR_USED const $mtid* in_msg_ptr;
GEM5_VAR_USED const $mtid* in_msg_ptr;
in_msg_ptr = dynamic_cast<const $mtid *>(($qcode).${{self.method}}());
if (in_msg_ptr == NULL) {
// If the cast fails, this is the wrong inport (wrong message type).

2
src/mem/slicc/symbols/StateMachine.py
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@@ -601,7 +601,7 @@ void
$c_ident::initNetQueues()
{
MachineType machine_type = string_to_MachineType("${{self.ident}}");
M5_VAR_USED int base = MachineType_base_number(machine_type);
GEM5_VAR_USED int base = MachineType_base_number(machine_type);
''')
code.indent()