diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index c724a79afd..aa1bae55b7 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -517,7 +517,7 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) saved_cpsr.v = tc->readCCReg(CCREG_V); saved_cpsr.ge = tc->readCCReg(CCREG_GE); - M5_VAR_USED Addr curPc = tc->pcState().pc(); + GEM5_VAR_USED Addr curPc = tc->pcState().pc(); ITSTATE it = tc->pcState().itstate(); saved_cpsr.it2 = it.top6; saved_cpsr.it1 = it.bottom2; @@ -525,7 +525,7 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) // if we have a valid instruction then use it to annotate this fault with // extra information. This is used to generate the correct fault syndrome // information - M5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst); + GEM5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst); // Ensure Secure state if initially in Monitor mode if (have_security && saved_cpsr.mode == MODE_MON) { @@ -703,7 +703,7 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) // If we have a valid instruction then use it to annotate this fault with // extra information. This is used to generate the correct fault syndrome // information - M5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst); + GEM5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst); // Set PC to start of exception handler Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL, true); @@ -755,7 +755,7 @@ Reset::getVector(ThreadContext *tc) Addr base; // Check for invalid modes - M5_VAR_USED CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); + GEM5_VAR_USED CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON); assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); @@ -1069,7 +1069,7 @@ AbortFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) // See ARM ARM B3-1416 bool override_LPAE = false; TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); - M5_VAR_USED TTBCR ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); + GEM5_VAR_USED TTBCR ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); if (ttbcr_s.eae) { override_LPAE = true; } else { diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index e20aef9418..6b1070b095 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -560,7 +560,7 @@ VldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst, unsigned eBytes = (1 << size); unsigned loadSize = eBytes * elems; - M5_VAR_USED unsigned loadRegs = + GEM5_VAR_USED unsigned loadRegs = (loadSize + sizeof(uint32_t) - 1) / sizeof(uint32_t); assert(loadRegs > 0 && loadRegs <= 4); @@ -924,7 +924,7 @@ VstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst, unsigned eBytes = (1 << size); unsigned storeSize = eBytes * elems; - M5_VAR_USED unsigned storeRegs = + GEM5_VAR_USED unsigned storeRegs = (storeSize + sizeof(uint32_t) - 1) / sizeof(uint32_t); assert(storeRegs > 0 && storeRegs <= 4); diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index 46a046becf..11df936cc7 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -83,16 +83,16 @@ let {{ "logic": '0' } - immOp2 = "M5_VAR_USED uint64_t secOp = imm;" - sRegOp2 = "M5_VAR_USED uint64_t secOp = " + \ + immOp2 = "GEM5_VAR_USED uint64_t secOp = imm;" + sRegOp2 = "GEM5_VAR_USED uint64_t secOp = " + \ "shiftReg64(Op264, shiftAmt, shiftType, intWidth);" - eRegOp2 = "M5_VAR_USED uint64_t secOp = " + \ + eRegOp2 = "GEM5_VAR_USED uint64_t secOp = " + \ "extendReg64(Op264, extendType, shiftAmt, intWidth);" def buildDataWork(mnem, code, flagType, suffix, buildCc, buildNonCc, base, templateBase): code = ''' - M5_VAR_USED uint64_t resTemp = 0; + GEM5_VAR_USED uint64_t resTemp = 0; ''' + code ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType]) Name = mnem.capitalize() + suffix @@ -577,9 +577,9 @@ let {{ def condCompCode(flagType, op, imm): ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType]) - opDecl = "M5_VAR_USED uint64_t secOp = imm;" + opDecl = "GEM5_VAR_USED uint64_t secOp = imm;" if not imm: - opDecl = "M5_VAR_USED uint64_t secOp = Op264;" + opDecl = "GEM5_VAR_USED uint64_t secOp = Op264;" return opDecl + ''' if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)) { uint64_t resTemp = Op164 ''' + op + ''' secOp; diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 52706e7798..7dc668cbbf 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -467,7 +467,7 @@ let {{ exec_output = "" singleSimpleCode = vfpEnabledCheckCode + ''' - M5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc; + GEM5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc; FpDest = %(op)s; ''' singleCode = singleSimpleCode + ''' @@ -488,7 +488,7 @@ let {{ "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" doubleCode = vfpEnabledCheckCode + ''' - M5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc; + GEM5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc; double dest = %(op)s; FpDestP0_uw = dblLow(dest); FpDestP1_uw = dblHi(dest); diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa index 76b0caea24..0a367953ba 100644 --- a/src/arch/arm/isa/insts/ldr64.isa +++ b/src/arch/arm/isa/insts/ldr64.isa @@ -201,7 +201,7 @@ let {{ accEpilogCode = None # Code that actually handles the access if self.flavor in ("dprefetch", "iprefetch", "mprefetch"): - accCode = 'M5_VAR_USED uint64_t temp = Mem%s;' + accCode = 'GEM5_VAR_USED uint64_t temp = Mem%s;' elif self.flavor == "fp": accEpilogCode = ''' ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest, diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index 64dcedda17..6e447af0ca 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -128,7 +128,7 @@ let {{ bitMask = (bitMask >> imm1) | (bitMask << (intWidth - imm1)); diff += intWidth; } - M5_VAR_USED uint64_t topBits = ~mask(diff+1); + GEM5_VAR_USED uint64_t topBits = ~mask(diff+1); uint64_t result = imm1 == 0 ? Op164 : (Op164 >> imm1) | (Op164 << (intWidth - imm1)); result &= bitMask; diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa index 8a4e724f6a..3f96fb09bd 100644 --- a/src/arch/arm/isa/insts/sve.isa +++ b/src/arch/arm/isa/insts/sve.isa @@ -2007,7 +2007,7 @@ let {{ destPred.reset(); for (unsigned i = 0; i < eCount; i++) { const Element& srcElem1 = AA64FpOp1_x[i]; - M5_VAR_USED %(src_elem_2_ty)s srcElem2 = %(src_elem_2)s; + GEM5_VAR_USED %(src_elem_2_ty)s srcElem2 = %(src_elem_2)s; bool destElem = false; if (tmpPred[i]) { %(op)s @@ -2703,7 +2703,7 @@ let {{ CondCodesC = !destPred.lastActive(GpOp, eCount); CondCodesV = 0;''' extraPrologCode = ''' - M5_VAR_USED auto& destPred = PDest;''' + GEM5_VAR_USED auto& destPred = PDest;''' baseClass = ('SvePredUnaryWImplicitSrcOp' if predType == PredType.NONE else 'SvePredUnaryWImplicitSrcPredOp') iop = ArmInstObjParams(name, 'Sve' + Name, baseClass, @@ -2722,7 +2722,7 @@ let {{ global header_output, exec_output, decoders code = sveEnabledCheckCode + op extraPrologCode = ''' - M5_VAR_USED auto& destPred = Ffr;''' + GEM5_VAR_USED auto& destPred = Ffr;''' baseClass = ('SveWImplicitSrcDstOp' if isSetFfr else 'SvePredUnaryWImplicitDstOp') iop = ArmInstObjParams(name, 'Sve' + Name, baseClass, diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index ca9e25a9cb..fad4ac9065 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -1164,7 +1164,7 @@ def template LoadRegConstructor {{ { %(set_reg_idx_arr)s; %(constructor)s; - M5_VAR_USED bool conditional = false; + GEM5_VAR_USED bool conditional = false; if (!(condCode == COND_AL || condCode == COND_UC)) { conditional = true; for (int x = 0; x < _numDestRegs; x++) { @@ -1231,7 +1231,7 @@ def template LoadImmConstructor {{ { %(set_reg_idx_arr)s; %(constructor)s; - M5_VAR_USED bool conditional = false; + GEM5_VAR_USED bool conditional = false; if (!(condCode == COND_AL || condCode == COND_UC)) { conditional = true; for (int x = 0; x < _numDestRegs; x++) { diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa index 9b1ab84022..a9788c49a2 100644 --- a/src/arch/arm/isa/templates/sve_mem.isa +++ b/src/arch/arm/isa/templates/sve_mem.isa @@ -157,7 +157,7 @@ def template SveContigLoadExecute {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -192,7 +192,7 @@ def template SveContigLoadInitiateAcc {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -217,7 +217,7 @@ def template SveContigLoadCompleteAcc {{ %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -247,7 +247,7 @@ def template SveContigStoreExecute {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -285,7 +285,7 @@ def template SveContigStoreInitiateAcc {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -329,7 +329,7 @@ def template SveLoadAndReplExecute {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -361,7 +361,7 @@ def template SveLoadAndReplInitiateAcc {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; %(op_src_decl)s; %(op_rd)s; @@ -386,7 +386,7 @@ def template SveLoadAndReplCompleteAcc {{ ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -585,7 +585,7 @@ def template SveGatherLoadMicroopExecute {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; %(op_decl)s; %(op_rd)s; @@ -634,7 +634,7 @@ def template SveGatherLoadMicroopInitiateAcc {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; %(op_src_decl)s; %(op_rd)s; @@ -675,7 +675,7 @@ def template SveGatherLoadMicroopCompleteAcc {{ %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const { - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; %(op_decl)s; %(op_rd)s; @@ -702,7 +702,7 @@ def template SveScatterStoreMicroopExecute {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; %(op_decl)s; %(op_rd)s; @@ -733,7 +733,7 @@ def template SveScatterStoreMicroopInitiateAcc {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; %(op_decl)s; %(op_rd)s; @@ -806,7 +806,7 @@ def template SveFirstFaultWritebackMicroopExecute {{ %(class_name)s%(tpl_args)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; %(op_decl)s; %(op_rd)s; @@ -989,7 +989,7 @@ def template SveStructLoadExecute {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -1023,7 +1023,7 @@ def template SveStructLoadInitiateAcc {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -1049,7 +1049,7 @@ def template SveStructLoadCompleteAcc {{ ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -1082,7 +1082,7 @@ def template SveStructStoreExecute {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); @@ -1120,7 +1120,7 @@ def template SveStructStoreInitiateAcc {{ { Addr EA; Fault fault = NoFault; - M5_VAR_USED bool aarch64 = true; + GEM5_VAR_USED bool aarch64 = true; unsigned eCount = ArmStaticInst::getCurSveVecLen(xc->tcBase()); diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index bea1e1636a..84ad948fbc 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -814,7 +814,7 @@ TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, // Cache clean operations require read permissions to the specified VA bool is_write = !req->isCacheClean() && mode == Write; bool is_atomic = req->isAtomic(); - M5_VAR_USED bool is_priv = isPriv && !(flags & UserMode); + GEM5_VAR_USED bool is_priv = isPriv && !(flags & UserMode); updateMiscReg(tc, curTranType); diff --git a/src/arch/isa_parser/isa_parser.py b/src/arch/isa_parser/isa_parser.py index 3c6f63d427..1e94a20228 100755 --- a/src/arch/isa_parser/isa_parser.py +++ b/src/arch/isa_parser/isa_parser.py @@ -133,7 +133,7 @@ class Template(object): if operands.predRead: myDict['op_decl'] += 'uint8_t _sourceIndex = 0;\n' if operands.predWrite: - myDict['op_decl'] += 'M5_VAR_USED uint8_t _destIndex = 0;\n' + myDict['op_decl'] += 'GEM5_VAR_USED uint8_t _destIndex = 0;\n' is_src = lambda op: op.is_src is_dest = lambda op: op.is_dest diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc index 0e6ea3f91b..a48982663f 100644 --- a/src/arch/mips/interrupts.cc +++ b/src/arch/mips/interrupts.cc @@ -145,8 +145,8 @@ Interrupts::getInterrupt() { assert(checkInterrupts()); - M5_VAR_USED StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); - M5_VAR_USED CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); + GEM5_VAR_USED StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); + GEM5_VAR_USED CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n", (unsigned)status.im, (unsigned)cause.ip); diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index 267d5e838f..431f174102 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -407,7 +407,7 @@ def template MiscExecute {{ Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { - M5_VAR_USED Addr EA = 0; + GEM5_VAR_USED Addr EA = 0; Fault fault = NoFault; %(fp_enable_check)s; diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 6e32caad60..97cae4133b 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -111,7 +111,7 @@ def template ThreadRegisterExecute {{ ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - M5_VAR_USED int64_t data; + GEM5_VAR_USED int64_t data; %(op_decl)s; %(op_rd)s; diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index 1b2500c5d9..8e6567dfda 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -112,7 +112,7 @@ def template LoadCompleteAcc {{ ExecContext *xc, Trace::InstRecord *traceData) const { - M5_VAR_USED Addr EA; + GEM5_VAR_USED Addr EA; Fault fault = NoFault; %(op_decl)s; diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index 6006c7133d..2ac3e9fcdb 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -53,7 +53,7 @@ namespace RiscvISA { -M5_VAR_USED const std::array MiscRegNames = {{ +GEM5_VAR_USED const std::array MiscRegNames = {{ [MISCREG_PRV] = "PRV", [MISCREG_ISA] = "ISA", [MISCREG_VENDORID] = "VENDORID", diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 408c5c4839..9c47a488ca 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -813,7 +813,7 @@ TrapInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) Process *p = tc->getProcessPtr(); - M5_VAR_USED SparcProcess *sp = dynamic_cast(p); + GEM5_VAR_USED SparcProcess *sp = dynamic_cast(p); assert(sp); auto *workload = dynamic_cast(tc->getSystemPtr()->workload); diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index 24c61be9e9..b9e499c29e 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -213,7 +213,7 @@ let {{ Macroop * macroop = dynamic_cast(curMacroop.get()); const ExtMachInst &machInst = macroop ? macroop->getExtMachInst() : dummyExtMachInst; - M5_VAR_USED const EmulEnv &env = + GEM5_VAR_USED const EmulEnv &env = macroop ? macroop->getEmulEnv() : dummyEmulEnv; using namespace RomLabels; return %s; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 15d5e60790..8e16a4ca07 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -50,7 +50,7 @@ def template MicroRegOpExecute {{ %(op_decl)s; %(op_rd)s; - M5_VAR_USED RegVal result; + GEM5_VAR_USED RegVal result; if (%(cond_check)s) { %(code)s; diff --git a/src/arch/x86/ldstflags.hh b/src/arch/x86/ldstflags.hh index e467f7b672..61c93899ee 100644 --- a/src/arch/x86/ldstflags.hh +++ b/src/arch/x86/ldstflags.hh @@ -46,7 +46,7 @@ */ namespace X86ISA { - M5_VAR_USED const Request::FlagsType SegmentFlagMask = mask(4); + GEM5_VAR_USED const Request::FlagsType SegmentFlagMask = mask(4); const int FlagShift = 4; enum FlagBit { diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index bdcc92b2c0..c1ea6f841e 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -141,7 +141,7 @@ ElfObject::ElfObject(ImageFileDataPtr ifd) : ObjectFile(ifd) "No loadable segments in '%s'. ELF file corrupted?\n", imageData->filename()); - for (M5_VAR_USED auto &seg: image.segments()) + for (GEM5_VAR_USED auto &seg: image.segments()) DPRINTFR(Loader, "%s\n", seg); // We will actually read the sections when we need to load them diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc index cfb60dfd0a..4c54e64c39 100644 --- a/src/base/remote_gdb.cc +++ b/src/base/remote_gdb.cc @@ -441,7 +441,7 @@ BaseRemoteGDB::detach() void BaseRemoteGDB::addThreadContext(ThreadContext *_tc) { - M5_VAR_USED auto it_success = threads.insert({_tc->contextId(), _tc}); + GEM5_VAR_USED auto it_success = threads.insert({_tc->contextId(), _tc}); assert(it_success.second); // If no ThreadContext is current selected, select this one. if (!tc) diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc index 459adae9d3..13518bdc26 100644 --- a/src/base/stats/group.cc +++ b/src/base/stats/group.cc @@ -67,7 +67,7 @@ Group::regStats() for (auto &g : statGroups) { if (Debug::Stats) { - M5_VAR_USED const SimObject *so = + GEM5_VAR_USED const SimObject *so = dynamic_cast(this); DPRINTF(Stats, "%s: regStats in group %s\n", so ? so->name() : "?", diff --git a/src/base/vnc/vncserver.cc b/src/base/vnc/vncserver.cc index a2d410587d..3417fa5f12 100644 --- a/src/base/vnc/vncserver.cc +++ b/src/base/vnc/vncserver.cc @@ -376,7 +376,7 @@ VncServer::checkProtocolVersion() { assert(curState == WaitForProtocolVersion); - M5_VAR_USED size_t len; + GEM5_VAR_USED size_t len; char version_string[13]; // Null terminate the message so it's easier to work with diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc index 82165be4b1..6edbffd8fb 100644 --- a/src/cpu/minor/fetch1.cc +++ b/src/cpu/minor/fetch1.cc @@ -390,7 +390,7 @@ void Fetch1::minorTraceResponseLine(const std::string &name, Fetch1::FetchRequestPtr response) const { - M5_VAR_USED const RequestPtr &request = response->request; + GEM5_VAR_USED const RequestPtr &request = response->request; if (response->packet && response->packet->isError()) { MINORLINE(this, "id=F;%s vaddr=0x%x fault=\"error packet\"\n", diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc index 0b6270916a..cfd1fd2756 100644 --- a/src/cpu/minor/lsq.cc +++ b/src/cpu/minor/lsq.cc @@ -78,7 +78,7 @@ LSQ::LSQRequest::tryToSuppressFault() SimpleThread &thread = *port.cpu.threads[inst->id.threadId]; TheISA::PCState old_pc = thread.pcState(); ExecContext context(port.cpu, thread, port.execute, inst, zeroReg); - M5_VAR_USED Fault fault = inst->translationFault; + GEM5_VAR_USED Fault fault = inst->translationFault; // Give the instruction a chance to suppress a translation fault inst->translationFault = inst->staticInst->initiateAcc(&context, nullptr); @@ -334,7 +334,7 @@ LSQ::SplitDataRequest::finish(const Fault &fault_, const RequestPtr &request_, { port.numAccessesInDTLB--; - M5_VAR_USED unsigned int expected_fragment_index = + GEM5_VAR_USED unsigned int expected_fragment_index = numTranslatedFragments; numInTranslationFragments--; @@ -475,7 +475,7 @@ LSQ::SplitDataRequest::makeFragmentRequests() for (unsigned int fragment_index = 0; fragment_index < numFragments; fragment_index++) { - M5_VAR_USED bool is_last_fragment = false; + GEM5_VAR_USED bool is_last_fragment = false; if (fragment_addr == base_addr) { /* First fragment */ diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 88536d0099..d74c858fcd 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -707,7 +707,7 @@ DefaultCommit::tick() // will be active. _nextStatus = Active; - M5_VAR_USED const DynInstPtr &inst = rob->readHeadInst(tid); + GEM5_VAR_USED const DynInstPtr &inst = rob->readHeadInst(tid); DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of" " ROB and ready to commit\n", diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index cddb1d5b9a..624149e4b7 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -683,7 +683,7 @@ LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, // This comming request can be either load, store or atomic. // Atomic request has a corresponding pointer to its atomic memory // operation - M5_VAR_USED bool isAtomic = !isLoad && amo_op; + GEM5_VAR_USED bool isAtomic = !isLoad && amo_op; ThreadID tid = cpu->contextToThread(inst->contextId()); auto cacheLineSize = cpu->cacheLineSize(); diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh index 7a97cf7c5c..330640c88e 100644 --- a/src/cpu/o3/mem_dep_unit_impl.hh +++ b/src/cpu/o3/mem_dep_unit_impl.hh @@ -270,7 +270,7 @@ MemDepUnit::insert(const DynInstPtr &inst) } else { // Otherwise make the instruction dependent on the store/barrier. DPRINTF(MemDepUnit, "Adding to dependency list\n"); - for (M5_VAR_USED auto producing_store : producing_stores) + for (GEM5_VAR_USED auto producing_store : producing_stores) DPRINTF(MemDepUnit, "\tinst PC %s is dependent on [sn:%lli].\n", inst->pcState(), producing_store); diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc index b45c956080..be19421c9b 100644 --- a/src/cpu/pred/bpred_unit.cc +++ b/src/cpu/pred/bpred_unit.cc @@ -111,7 +111,7 @@ BPredUnit::drainSanityCheck() const { // We shouldn't have any outstanding requests when we resume from // a drained system. - for (M5_VAR_USED const auto& ph : predHist) + for (GEM5_VAR_USED const auto& ph : predHist) assert(ph.empty()); } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 6891746d18..d5f76aad47 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -166,7 +166,7 @@ void TimingSimpleCPU::switchOut() { SimpleExecContext& t_info = *threadInfo[curThread]; - M5_VAR_USED SimpleThread* thread = t_info.thread; + GEM5_VAR_USED SimpleThread* thread = t_info.thread; // hardware transactional memory // Cannot switch out the CPU in the middle of a transaction @@ -937,7 +937,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) // hardware transactional memory SimpleExecContext *t_info = threadInfo[curThread]; - M5_VAR_USED const bool is_htm_speculative = + GEM5_VAR_USED const bool is_htm_speculative = t_info->inHtmTransactionalState(); // received a response from the dcache: complete the load or store diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index 88cc68015a..ad4f21a025 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -243,7 +243,7 @@ MemTest::tick() if (cmd < percentReads) { // start by ensuring there is a reference value if we have not // seen this address before - M5_VAR_USED uint8_t ref_data = 0; + GEM5_VAR_USED uint8_t ref_data = 0; auto ref = referenceData.find(req->getPaddr()); if (ref == referenceData.end()) { referenceData[req->getPaddr()] = 0; diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc index bf532bff7b..7f7439ad8b 100644 --- a/src/cpu/trace/trace_cpu.cc +++ b/src/cpu/trace/trace_cpu.cc @@ -811,7 +811,7 @@ TraceCPU::ElasticDataGen::printReadyList() DPRINTF(TraceCPUData, "Printing readyList:\n"); while (itr != readyList.end()) { auto graph_itr = depGraph.find(itr->seqNum); - M5_VAR_USED GraphNode* node_ptr = graph_itr->second; + GEM5_VAR_USED GraphNode* node_ptr = graph_itr->second; DPRINTFR(TraceCPUData, "\t%lld(%s), %lld\n", itr->seqNum, node_ptr->typeToStr(), itr->execTick); itr++; @@ -1322,7 +1322,7 @@ TraceCPU::ElasticDataGen::GraphNode::removeDepOnInst(NodeSeqNum done_seq_num) // If it is not an rob dependency then it must be a register dependency // If the register dependency is not found, it violates an assumption // and must be caught by assert. - M5_VAR_USED bool regdep_found = removeRegDep(done_seq_num); + GEM5_VAR_USED bool regdep_found = removeRegDep(done_seq_num); assert(regdep_found); } // Return true if the node is dependency free diff --git a/src/dev/amdgpu/amdgpu_device.cc b/src/dev/amdgpu/amdgpu_device.cc index 02e6124384..e409be5542 100644 --- a/src/dev/amdgpu/amdgpu_device.cc +++ b/src/dev/amdgpu/amdgpu_device.cc @@ -92,7 +92,7 @@ AMDGPUDevice::getAddrRanges() const Tick AMDGPUDevice::readConfig(PacketPtr pkt) { - M5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE; + GEM5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE; DPRINTF(AMDGPUDevice, "Read Config: from offset: %#x size: %#x " "data: %#x\n", offset, pkt->getSize(), config.data[offset]); @@ -102,7 +102,7 @@ AMDGPUDevice::readConfig(PacketPtr pkt) Tick AMDGPUDevice::writeConfig(PacketPtr pkt) { - M5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE; + GEM5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE; DPRINTF(AMDGPUDevice, "Write Config: from offset: %#x size: %#x " "data: %#x\n", offset, pkt->getSize(), pkt->getUintX(ByteOrder::little)); diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc index df4969d83e..b79d6f7f99 100644 --- a/src/dev/arm/gic_v2.cc +++ b/src/dev/arm/gic_v2.cc @@ -390,7 +390,7 @@ GicV2::writeDistributor(PacketPtr pkt) const ContextID ctx = pkt->req->contextId(); const size_t data_sz = pkt->getSize(); - M5_VAR_USED uint32_t pkt_data; + GEM5_VAR_USED uint32_t pkt_data; switch (data_sz) { case 1: diff --git a/src/dev/hsa/hsa_packet_processor.cc b/src/dev/hsa/hsa_packet_processor.cc index eeb64da4c9..8749aa7cfd 100644 --- a/src/dev/hsa/hsa_packet_processor.cc +++ b/src/dev/hsa/hsa_packet_processor.cc @@ -127,7 +127,7 @@ HSAPacketProcessor::write(Packet *pkt) assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); // TODO: How to get pid?? - M5_VAR_USED Addr daddr = pkt->getAddr() - pioAddr; + GEM5_VAR_USED Addr daddr = pkt->getAddr() - pioAddr; DPRINTF(HSAPacketProcessor, "%s: write of size %d to reg-offset %d (0x%x)\n", @@ -265,7 +265,7 @@ void HSAPacketProcessor::CmdQueueCmdDmaEvent::process() { uint32_t rl_idx = series_ctx->rl_idx; - M5_VAR_USED AQLRingBuffer *aqlRingBuffer = + GEM5_VAR_USED AQLRingBuffer *aqlRingBuffer = hsaPP->regdQList[rl_idx]->qCntxt.aqlBuf; HSAQueueDescriptor* qDesc = hsaPP->regdQList[rl_idx]->qCntxt.qDesc; @@ -608,7 +608,7 @@ HSAPacketProcessor::getCommandsFromHost(int pid, uint32_t rl_idx) void HSAPacketProcessor::displayQueueDescriptor(int pid, uint32_t rl_idx) { - M5_VAR_USED HSAQueueDescriptor* qDesc = regdQList[rl_idx]->qCntxt.qDesc; + GEM5_VAR_USED HSAQueueDescriptor* qDesc = regdQList[rl_idx]->qCntxt.qDesc; DPRINTF(HSAPacketProcessor, "%s: pid[%d], basePointer[0x%lx], dBPointer[0x%lx], " "writeIndex[0x%x], readIndex[0x%x], size(bytes)[0x%x]\n", diff --git a/src/dev/hsa/hw_scheduler.cc b/src/dev/hsa/hw_scheduler.cc index 00dff99984..be7b369563 100644 --- a/src/dev/hsa/hw_scheduler.cc +++ b/src/dev/hsa/hw_scheduler.cc @@ -113,7 +113,7 @@ HWScheduler::registerNewQueue(uint64_t hostReadIndexPointer, // Check if this newly created queue can be directly mapped // to registered queue list - M5_VAR_USED bool register_q = mapQIfSlotAvlbl(queue_id, aql_buf, q_desc); + GEM5_VAR_USED bool register_q = mapQIfSlotAvlbl(queue_id, aql_buf, q_desc); schedWakeup(); DPRINTF(HSAPacketProcessor, "%s: offset = %p, qID = %d, is_regd = %s, AL size %d\n", diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc index 4a38905465..9eecfe62c5 100644 --- a/src/dev/net/sinic.cc +++ b/src/dev/net/sinic.cc @@ -219,7 +219,7 @@ Device::read(PacketPtr pkt) prepareRead(cpu, index); - M5_VAR_USED uint64_t value = 0; + GEM5_VAR_USED uint64_t value = 0; if (pkt->getSize() == 4) { uint32_t reg = regData32(raddr); pkt->setLE(reg); diff --git a/src/dev/net/tcp_iface.cc b/src/dev/net/tcp_iface.cc index 014844280d..5d75765f74 100644 --- a/src/dev/net/tcp_iface.cc +++ b/src/dev/net/tcp_iface.cc @@ -251,7 +251,7 @@ TCPIface::connect() TCPIface::~TCPIface() { - M5_VAR_USED int ret; + GEM5_VAR_USED int ret; ret = close(sock); assert(ret == 0); diff --git a/src/dev/pci/copy_engine.cc b/src/dev/pci/copy_engine.cc index 48326cf2c2..c491d66bc5 100644 --- a/src/dev/pci/copy_engine.cc +++ b/src/dev/pci/copy_engine.cc @@ -306,19 +306,19 @@ CopyEngine::write(PacketPtr pkt) /// if (size == sizeof(uint64_t)) { - M5_VAR_USED uint64_t val = pkt->getLE(); + GEM5_VAR_USED uint64_t val = pkt->getLE(); DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val); } else if (size == sizeof(uint32_t)) { - M5_VAR_USED uint32_t val = pkt->getLE(); + GEM5_VAR_USED uint32_t val = pkt->getLE(); DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val); } else if (size == sizeof(uint16_t)) { - M5_VAR_USED uint16_t val = pkt->getLE(); + GEM5_VAR_USED uint16_t val = pkt->getLE(); DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val); } else if (size == sizeof(uint8_t)) { - M5_VAR_USED uint8_t val = pkt->getLE(); + GEM5_VAR_USED uint8_t val = pkt->getLE(); DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val); } else { diff --git a/src/dev/virtio/pci.cc b/src/dev/virtio/pci.cc index 003cbf563c..8f06aa6a18 100644 --- a/src/dev/virtio/pci.cc +++ b/src/dev/virtio/pci.cc @@ -65,7 +65,7 @@ PciVirtIO::~PciVirtIO() Tick PciVirtIO::read(PacketPtr pkt) { - M5_VAR_USED const unsigned size(pkt->getSize()); + GEM5_VAR_USED const unsigned size(pkt->getSize()); int bar; Addr offset; if (!getBAR(pkt->getAddr(), bar, offset)) @@ -146,7 +146,7 @@ PciVirtIO::read(PacketPtr pkt) Tick PciVirtIO::write(PacketPtr pkt) { - M5_VAR_USED const unsigned size(pkt->getSize()); + GEM5_VAR_USED const unsigned size(pkt->getSize()); int bar; Addr offset; if (!getBAR(pkt->getAddr(), bar, offset)) diff --git a/src/gpu-compute/compute_unit.cc b/src/gpu-compute/compute_unit.cc index cff04c15f7..b845151dbe 100644 --- a/src/gpu-compute/compute_unit.cc +++ b/src/gpu-compute/compute_unit.cc @@ -352,7 +352,7 @@ ComputeUnit::startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk, // set the wavefront context to have a pointer to this section of the LDS w->ldsChunk = ldsChunk; - M5_VAR_USED int32_t refCount = + GEM5_VAR_USED int32_t refCount = lds.increaseRefCounter(w->dispatchId, w->wgId); DPRINTF(GPUDisp, "CU%d: increase ref ctr wg[%d] to [%d]\n", cu_id, w->wgId, refCount); @@ -956,7 +956,7 @@ ComputeUnit::DataPort::recvReqRetry() for (int i = 0; i < len; ++i) { PacketPtr pkt = retries.front().first; - M5_VAR_USED GPUDynInstPtr gpuDynInst = retries.front().second; + GEM5_VAR_USED GPUDynInstPtr gpuDynInst = retries.front().second; DPRINTF(GPUMem, "CU%d: WF[%d][%d]: retry mem inst addr %#x\n", computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, pkt->req->getPaddr()); @@ -990,7 +990,7 @@ ComputeUnit::SQCPort::recvReqRetry() for (int i = 0; i < len; ++i) { PacketPtr pkt = retries.front().first; - M5_VAR_USED Wavefront *wavefront = retries.front().second; + GEM5_VAR_USED Wavefront *wavefront = retries.front().second; DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: retrying FETCH addr %#x\n", computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId, pkt->req->getPaddr()); @@ -1402,7 +1402,7 @@ ComputeUnit::DTLBPort::recvTimingResp(PacketPtr pkt) DTLBPort::SenderState *sender_state = safe_cast(translation_state->saved); - M5_VAR_USED Wavefront *w = + GEM5_VAR_USED Wavefront *w = computeUnit->wfList[sender_state->_gpuDynInst->simdId] [sender_state->_gpuDynInst->wfSlotId]; @@ -1571,7 +1571,7 @@ ComputeUnit::DataPort::processMemReqEvent(PacketPtr pkt) { SenderState *sender_state = safe_cast(pkt->senderState); GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; - M5_VAR_USED ComputeUnit *compute_unit = computeUnit; + GEM5_VAR_USED ComputeUnit *compute_unit = computeUnit; if (!(sendTimingReq(pkt))) { retries.push_back(std::make_pair(pkt, gpuDynInst)); @@ -1600,7 +1600,7 @@ ComputeUnit::ScalarDataPort::MemReqEvent::process() { SenderState *sender_state = safe_cast(pkt->senderState); GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; - M5_VAR_USED ComputeUnit *compute_unit = scalarDataPort.computeUnit; + GEM5_VAR_USED ComputeUnit *compute_unit = scalarDataPort.computeUnit; if (!(scalarDataPort.sendTimingReq(pkt))) { scalarDataPort.retries.push_back(pkt); @@ -1640,7 +1640,7 @@ ComputeUnit::DTLBPort::recvReqRetry() for (int i = 0; i < len; ++i) { PacketPtr pkt = retries.front(); - M5_VAR_USED Addr vaddr = pkt->req->getVaddr(); + GEM5_VAR_USED Addr vaddr = pkt->req->getVaddr(); DPRINTF(GPUTLB, "CU%d: retrying D-translaton for address%#x", vaddr); if (!sendTimingReq(pkt)) { @@ -1679,7 +1679,7 @@ ComputeUnit::ScalarDTLBPort::recvTimingResp(PacketPtr pkt) GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; delete pkt->senderState; - M5_VAR_USED Wavefront *w = gpuDynInst->wavefront(); + GEM5_VAR_USED Wavefront *w = gpuDynInst->wavefront(); DPRINTF(GPUTLB, "CU%d: WF[%d][%d][wv=%d]: scalar DTLB port received " "translation: PA %#x -> %#x\n", computeUnit->cu_id, w->simdId, @@ -1718,7 +1718,7 @@ ComputeUnit::ScalarDTLBPort::recvTimingResp(PacketPtr pkt) bool ComputeUnit::ITLBPort::recvTimingResp(PacketPtr pkt) { - M5_VAR_USED Addr line = pkt->req->getPaddr(); + GEM5_VAR_USED Addr line = pkt->req->getPaddr(); DPRINTF(GPUTLB, "CU%d: ITLBPort received %#x->%#x\n", computeUnit->cu_id, pkt->req->getVaddr(), line); @@ -1784,7 +1784,7 @@ ComputeUnit::ITLBPort::recvReqRetry() for (int i = 0; i < len; ++i) { PacketPtr pkt = retries.front(); - M5_VAR_USED Addr vaddr = pkt->req->getVaddr(); + GEM5_VAR_USED Addr vaddr = pkt->req->getVaddr(); DPRINTF(GPUTLB, "CU%d: retrying I-translaton for address%#x", vaddr); if (!sendTimingReq(pkt)) { @@ -2037,7 +2037,7 @@ ComputeUnit::LDSPort::sendTimingReq(PacketPtr pkt) dynamic_cast(pkt->senderState); fatal_if(!sender_state, "packet without a valid sender state"); - M5_VAR_USED GPUDynInstPtr gpuDynInst = sender_state->getMemInst(); + GEM5_VAR_USED GPUDynInstPtr gpuDynInst = sender_state->getMemInst(); if (isStalled()) { fatal_if(retries.empty(), "must have retries waiting to be stalled"); diff --git a/src/gpu-compute/gpu_compute_driver.cc b/src/gpu-compute/gpu_compute_driver.cc index ac42752503..c596fd0a10 100644 --- a/src/gpu-compute/gpu_compute_driver.cc +++ b/src/gpu-compute/gpu_compute_driver.cc @@ -582,7 +582,7 @@ GPUComputeDriver::ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf) assert(isdGPU); assert((args->va_addr % TheISA::PageBytes) == 0); - M5_VAR_USED Addr mmap_offset = 0; + GEM5_VAR_USED Addr mmap_offset = 0; Request::CacheCoherenceFlags mtype = defaultMtype; Addr pa_addr = 0; diff --git a/src/gpu-compute/schedule_stage.cc b/src/gpu-compute/schedule_stage.cc index ace6d0c3f5..f51a57b56d 100644 --- a/src/gpu-compute/schedule_stage.cc +++ b/src/gpu-compute/schedule_stage.cc @@ -758,7 +758,7 @@ ScheduleStage::reserveResources() // that we've reserved a global and local memory unit. Thus, // we need to mark the latter execution unit as not available. if (execUnitIds.size() > 1) { - M5_VAR_USED int lm_exec_unit = wf->localMem; + GEM5_VAR_USED int lm_exec_unit = wf->localMem; assert(toExecute.dispatchStatus(lm_exec_unit) == SKIP); } @@ -767,7 +767,7 @@ ScheduleStage::reserveResources() // Verify the GM pipe for this wave is ready to execute // and the wave in the GM pipe is the same as the wave // in the LM pipe - M5_VAR_USED int gm_exec_unit = wf->globalMem; + GEM5_VAR_USED int gm_exec_unit = wf->globalMem; assert(wf->wfDynId == toExecute .readyInst(gm_exec_unit)->wfDynId); assert(toExecute.dispatchStatus(gm_exec_unit) diff --git a/src/kern/linux/linux.cc b/src/kern/linux/linux.cc index e5b71446a7..103d1d164d 100644 --- a/src/kern/linux/linux.cc +++ b/src/kern/linux/linux.cc @@ -73,7 +73,7 @@ Linux::openSpecialFile(std::string path, Process *process, if (matched) { FILE *f = tmpfile(); int fd = fileno(f); - M5_VAR_USED size_t ret = fwrite(data.c_str(), 1, data.size(), f); + GEM5_VAR_USED size_t ret = fwrite(data.c_str(), 1, data.size(), f); assert(ret == data.size()); rewind(f); return fd; diff --git a/src/kern/system_events.cc b/src/kern/system_events.cc index a8dfc28ac5..83415a2b16 100644 --- a/src/kern/system_events.cc +++ b/src/kern/system_events.cc @@ -35,7 +35,7 @@ void SkipFuncBase::process(ThreadContext *tc) { - M5_VAR_USED TheISA::PCState oldPC = tc->pcState(); + GEM5_VAR_USED TheISA::PCState oldPC = tc->pcState(); returnFromFuncIn(tc); diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc index 788291fbbd..dbbc767ea6 100644 --- a/src/learning_gem5/part2/simple_cache.cc +++ b/src/learning_gem5/part2/simple_cache.cc @@ -229,7 +229,7 @@ SimpleCache::handleResponse(PacketPtr pkt) DPRINTF(SimpleCache, "Copying data from new packet to old\n"); // We had to upgrade a previous packet. We can functionally deal with // the cache access now. It better be a hit. - M5_VAR_USED bool hit = accessFunctional(originalPacket); + GEM5_VAR_USED bool hit = accessFunctional(originalPacket); panic_if(!hit, "Should always hit after inserting"); originalPacket->makeResponse(); delete pkt; // We may need to delay this, I'm not sure. diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 772dc862aa..375fd300b1 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -896,7 +896,7 @@ BaseCache::updateCompressionData(CacheBlk *&blk, const uint64_t* data, // Get previous compressed size CompressionBlk* compression_blk = static_cast(blk); - M5_VAR_USED const std::size_t prev_size = compression_blk->getSizeBits(); + GEM5_VAR_USED const std::size_t prev_size = compression_blk->getSizeBits(); // If compressed size didn't change enough to modify its co-allocatability // there is nothing to do. Otherwise we may be facing a data expansion @@ -2418,7 +2418,7 @@ BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt) if (cache->system->bypassCaches()) { // Just forward the packet if caches are disabled. // @todo This should really enqueue the packet rather - M5_VAR_USED bool success = cache->memSidePort.sendTimingReq(pkt); + GEM5_VAR_USED bool success = cache->memSidePort.sendTimingReq(pkt); assert(success); return true; } else if (tryTiming(pkt)) { diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index d5c6b55f37..900cf48a39 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -449,7 +449,7 @@ Cache::recvTimingReq(PacketPtr pkt) // this express snoop travels towards the memory, and at // every crossbar it is snooped upwards thus reaching // every cache in the system - M5_VAR_USED bool success = memSidePort.sendTimingReq(snoop_pkt); + GEM5_VAR_USED bool success = memSidePort.sendTimingReq(snoop_pkt); // express snoops always succeed assert(success); @@ -992,7 +992,7 @@ Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, // responds in atomic mode, so remember a few things about the // original packet up front bool invalidate = pkt->isInvalidate(); - M5_VAR_USED bool needs_writable = pkt->needsWritable(); + GEM5_VAR_USED bool needs_writable = pkt->needsWritable(); // at the moment we could get an uncacheable write which does not // have the invalidate flag, and we need a suitable way of dealing @@ -1394,7 +1394,7 @@ Cache::sendMSHRQueuePacket(MSHR* mshr) // prefetchSquash first may result in the MSHR being // prematurely deallocated. if (snoop_pkt.cacheResponding()) { - M5_VAR_USED auto r = outstandingSnoop.insert(snoop_pkt.req); + GEM5_VAR_USED auto r = outstandingSnoop.insert(snoop_pkt.req); assert(r.second); // if we are getting a snoop response with no sharers it diff --git a/src/mem/cache/compressors/frequent_values.cc b/src/mem/cache/compressors/frequent_values.cc index 2806e31b12..f937ec41b2 100644 --- a/src/mem/cache/compressors/frequent_values.cc +++ b/src/mem/cache/compressors/frequent_values.cc @@ -141,7 +141,7 @@ FrequentValues::decompress(const CompressionData* comp_data, uint64_t* data) // its corresponding value, in order to make life easier we // search for the value and verify that the stored code // matches the table's - M5_VAR_USED const Encoder::Code code = + GEM5_VAR_USED const Encoder::Code code = encoder.encode(comp_chunk.value); // Either the value will be found and the codes match, or the diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index e14da13237..259d5add3b 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -110,7 +110,7 @@ void FALRU::invalidate(CacheBlk *blk) { // Erase block entry reference in the hash table - M5_VAR_USED auto num_erased = + GEM5_VAR_USED auto num_erased = tagHash.erase(std::make_pair(blk->getTag(), blk->isSecure())); // Sanity check; only one block reference should be erased diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc index 79ef629abc..a939e92708 100644 --- a/src/mem/coherent_xbar.cc +++ b/src/mem/coherent_xbar.cc @@ -638,7 +638,7 @@ CoherentXBar::recvTimingSnoopResp(PacketPtr pkt, PortID cpu_side_port_id) *memSidePorts[dest_port_id]); } - M5_VAR_USED bool success = + GEM5_VAR_USED bool success = memSidePorts[dest_port_id]->sendTimingSnoopResp(pkt); pktCount[cpu_side_port_id][dest_port_id]++; pktSize[cpu_side_port_id][dest_port_id] += pkt_size; @@ -858,7 +858,7 @@ CoherentXBar::recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id, // if this is the destination of the operation, the xbar // sends the responce to the cache clean operation only // after having encountered the cache clean request - M5_VAR_USED auto ret = outstandingCMO.emplace(pkt->id, nullptr); + GEM5_VAR_USED auto ret = outstandingCMO.emplace(pkt->id, nullptr); // in atomic mode we know that the WriteClean packet should // precede the clean request assert(ret.second); diff --git a/src/mem/dramsim2_wrapper.cc b/src/mem/dramsim2_wrapper.cc index f8cb4a4666..9e3a96185e 100644 --- a/src/mem/dramsim2_wrapper.cc +++ b/src/mem/dramsim2_wrapper.cc @@ -169,7 +169,7 @@ DRAMSim2Wrapper::canAccept() const void DRAMSim2Wrapper::enqueue(bool is_write, uint64_t addr) { - M5_VAR_USED bool success = dramsim->addTransaction(is_write, addr); + GEM5_VAR_USED bool success = dramsim->addTransaction(is_write, addr); assert(success); } diff --git a/src/mem/dramsim3_wrapper.cc b/src/mem/dramsim3_wrapper.cc index b37a93cc03..f45b2506c8 100644 --- a/src/mem/dramsim3_wrapper.cc +++ b/src/mem/dramsim3_wrapper.cc @@ -123,7 +123,7 @@ DRAMsim3Wrapper::canAccept(uint64_t addr, bool is_write) const void DRAMsim3Wrapper::enqueue(uint64_t addr, bool is_write) { - M5_VAR_USED bool success = dramsim->AddTransaction(addr, is_write); + GEM5_VAR_USED bool success = dramsim->AddTransaction(addr, is_write); assert(success); } diff --git a/src/mem/external_slave.cc b/src/mem/external_slave.cc index 16ac7aad65..50528124ce 100644 --- a/src/mem/external_slave.cc +++ b/src/mem/external_slave.cc @@ -97,7 +97,7 @@ Tick StubSlavePort::recvAtomic(PacketPtr packet) { if (Debug::ExternalPort) { - M5_VAR_USED unsigned int size = packet->getSize(); + GEM5_VAR_USED unsigned int size = packet->getSize(); DPRINTF(ExternalPort, "StubSlavePort: recvAtomic a: 0x%x size: %d" " data: ...\n", packet->getAddr(), size); diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index d088d296b5..b7cfd62feb 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -78,7 +78,7 @@ EmulationPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) new_vaddr, size); while (size > 0) { - M5_VAR_USED auto new_it = pTable.find(new_vaddr); + GEM5_VAR_USED auto new_it = pTable.find(new_vaddr); auto old_it = pTable.find(vaddr); assert(old_it != pTable.end() && new_it == pTable.end()); diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.cc b/src/mem/ruby/network/garnet/GarnetNetwork.cc index c260247120..9b69dd925a 100644 --- a/src/mem/ruby/network/garnet/GarnetNetwork.cc +++ b/src/mem/ruby/network/garnet/GarnetNetwork.cc @@ -128,7 +128,7 @@ GarnetNetwork::init() for (std::vector::const_iterator i= m_routers.begin(); i != m_routers.end(); ++i) { Router* router = safe_cast(*i); - M5_VAR_USED int router_id = + GEM5_VAR_USED int router_id = fault_model->declare_router(router->get_num_inports(), router->get_num_outports(), router->get_vc_per_vnet(), diff --git a/src/mem/ruby/network/garnet/RoutingUnit.cc b/src/mem/ruby/network/garnet/RoutingUnit.cc index 1a75f651b5..02be829f43 100644 --- a/src/mem/ruby/network/garnet/RoutingUnit.cc +++ b/src/mem/ruby/network/garnet/RoutingUnit.cc @@ -201,7 +201,7 @@ RoutingUnit::outportComputeXY(RouteInfo route, { PortDirection outport_dirn = "Unknown"; - M5_VAR_USED int num_rows = m_router->get_net_ptr()->getNumRows(); + GEM5_VAR_USED int num_rows = m_router->get_net_ptr()->getNumRows(); int num_cols = m_router->get_net_ptr()->getNumCols(); assert(num_rows > 0 && num_cols > 0); diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index 1436e9a883..e927620d8b 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -408,8 +408,8 @@ void CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const { uint64_t warmedUpBlocks = 0; - M5_VAR_USED uint64_t totalBlocks = (uint64_t)m_cache_num_sets * - (uint64_t)m_cache_assoc; + GEM5_VAR_USED uint64_t totalBlocks = (uint64_t)m_cache_num_sets * + (uint64_t)m_cache_assoc; for (int i = 0; i < m_cache_num_sets; i++) { for (int j = 0; j < m_cache_assoc; j++) { diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh index a1c8a82701..53687f1f3b 100644 --- a/src/mem/ruby/structures/PerfectCacheMemory.hh +++ b/src/mem/ruby/structures/PerfectCacheMemory.hh @@ -150,7 +150,7 @@ template inline void PerfectCacheMemory::deallocate(Addr address) { - M5_VAR_USED auto num_erased = m_map.erase(makeLineAddress(address)); + GEM5_VAR_USED auto num_erased = m_map.erase(makeLineAddress(address)); assert(num_erased == 1); } diff --git a/src/mem/ruby/system/GPUCoalescer.cc b/src/mem/ruby/system/GPUCoalescer.cc index c5c1c08ed0..2161ba3007 100644 --- a/src/mem/ruby/system/GPUCoalescer.cc +++ b/src/mem/ruby/system/GPUCoalescer.cc @@ -532,7 +532,7 @@ GPUCoalescer::hitCallback(CoalescedRequest* crequest, { PacketPtr pkt = crequest->getFirstPkt(); Addr request_address = pkt->getAddr(); - M5_VAR_USED Addr request_line_address = makeLineAddress(request_address); + GEM5_VAR_USED Addr request_line_address = makeLineAddress(request_address); RubyRequestType type = crequest->getRubyType(); diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index b47aaefca4..5961254331 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -206,7 +206,7 @@ RubyPort::PioResponsePort::recvTimingReq(PacketPtr pkt) if (it->contains(pkt->getAddr())) { // generally it is not safe to assume success here as // the port could be blocked - M5_VAR_USED bool success = + GEM5_VAR_USED bool success = ruby_port->request_ports[i]->sendTimingReq(pkt); assert(success); return true; @@ -373,7 +373,7 @@ RubyPort::MemResponsePort::recvFunctional(PacketPtr pkt) { DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); - M5_VAR_USED RubyPort *rp = static_cast(&owner); + GEM5_VAR_USED RubyPort *rp = static_cast(&owner); RubySystem *rs = rp->m_ruby_system; // Check for pio requests and directly send them to the dedicated @@ -600,7 +600,7 @@ RubyPort::PioResponsePort::getAddrRanges() const ranges.splice(ranges.begin(), ruby_port->request_ports[i]->getAddrRanges()); } - for (M5_VAR_USED const auto &r : ranges) + for (GEM5_VAR_USED const auto &r : ranges) DPRINTF(RubyPort, "%s\n", r.to_string()); return ranges; } diff --git a/src/mem/ruby/system/RubySystem.cc b/src/mem/ruby/system/RubySystem.cc index 18ebc7ff42..fcb407fd81 100644 --- a/src/mem/ruby/system/RubySystem.cc +++ b/src/mem/ruby/system/RubySystem.cc @@ -691,7 +691,7 @@ RubySystem::functionalWrite(PacketPtr pkt) DPRINTF(RubySystem, "Functional Write request for %#x\n", addr); - M5_VAR_USED uint32_t num_functional_writes = 0; + GEM5_VAR_USED uint32_t num_functional_writes = 0; // Only send functional requests within the same network. assert(requestorToNetwork.count(pkt->requestorId())); diff --git a/src/mem/slicc/ast/PeekStatementAST.py b/src/mem/slicc/ast/PeekStatementAST.py index 2ad182ff4f..babff3178f 100644 --- a/src/mem/slicc/ast/PeekStatementAST.py +++ b/src/mem/slicc/ast/PeekStatementAST.py @@ -61,7 +61,7 @@ class PeekStatementAST(StatementAST): code(''' { // Declare message - M5_VAR_USED const $mtid* in_msg_ptr; + GEM5_VAR_USED const $mtid* in_msg_ptr; in_msg_ptr = dynamic_cast(($qcode).${{self.method}}()); if (in_msg_ptr == NULL) { // If the cast fails, this is the wrong inport (wrong message type). diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 59e54a8994..747baccaed 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -601,7 +601,7 @@ void $c_ident::initNetQueues() { MachineType machine_type = string_to_MachineType("${{self.ident}}"); - M5_VAR_USED int base = MachineType_base_number(machine_type); + GEM5_VAR_USED int base = MachineType_base_number(machine_type); ''') code.indent() diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 766b722278..29350ea737 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -766,7 +766,7 @@ class MetaSimObject(type): # method, or the Dummy one. Either an implementation is # mandantory since this was shunted off to the dummy class, or # one is optional which will override this weak version. - code('M5_VAR_USED ${{cls.cxx_class}} *') + code('GEM5_VAR_USED ${{cls.cxx_class}} *') code('Dummy${cls}Shunt<${{cls.cxx_class}}>::Params::create() const') code('{') code(' return Dummy${cls}Shunt<${{cls.cxx_class}}>::') diff --git a/src/sim/guest_abi/dispatch.hh b/src/sim/guest_abi/dispatch.hh index 8f3a4ac036..2caa208b89 100644 --- a/src/sim/guest_abi/dispatch.hh +++ b/src/sim/guest_abi/dispatch.hh @@ -96,7 +96,7 @@ callFrom(ThreadContext *tc, typename ABI::State &state, template static void -dumpArgsFrom(std::ostream &os, M5_VAR_USED ThreadContext *tc, +dumpArgsFrom(std::ostream &os, GEM5_VAR_USED ThreadContext *tc, typename ABI::State &state) { int count = 0; diff --git a/src/sim/guest_abi/layout.hh b/src/sim/guest_abi/layout.hh index 6de04703e8..08840ec289 100644 --- a/src/sim/guest_abi/layout.hh +++ b/src/sim/guest_abi/layout.hh @@ -109,7 +109,8 @@ prepareForResult(ThreadContext *tc, typename ABI::State &state) template static inline void -prepareForArguments(M5_VAR_USED ThreadContext *tc, typename ABI::State &state) +prepareForArguments(GEM5_VAR_USED ThreadContext *tc, + typename ABI::State &state) { M5_FOR_EACH_IN_PACK(Preparer::prepare(tc, state)); } diff --git a/src/sim/system.cc b/src/sim/system.cc index 492bf63c61..7f81f5184b 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -179,7 +179,7 @@ System::Threads::quiesce(ContextID id) { auto &t = thread(id); # if THE_ISA != NULL_ISA - M5_VAR_USED BaseCPU *cpu = t.context->getCpuPtr(); + GEM5_VAR_USED BaseCPU *cpu = t.context->getCpuPtr(); DPRINTFS(Quiesce, cpu, "quiesce()\n"); # endif t.quiesce(); @@ -255,7 +255,7 @@ System::System(const Params &p) } // Get the generic system requestor IDs - M5_VAR_USED RequestorID tmp_id; + GEM5_VAR_USED RequestorID tmp_id; tmp_id = getRequestorId(this, "writebacks"); assert(tmp_id == Request::wbRequestorId); tmp_id = getRequestorId(this, "functional");