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misc: Replace M5_VAR_USED with GEM5_VAR_USED.

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Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Gabe Black
2021-05-08 20:23:10 -07:00
parent e55ae090b3
commit fb3befcc6d
69 changed files with 133 additions and 132 deletions
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4
src/dev/amdgpu/amdgpu_device.cc
View File

@@ -92,7 +92,7 @@ AMDGPUDevice::getAddrRanges() const
Tick
AMDGPUDevice::readConfig(PacketPtr pkt)
{
M5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
GEM5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
DPRINTF(AMDGPUDevice, "Read Config: from offset: %#x size: %#x "
"data: %#x\n", offset, pkt->getSize(), config.data[offset]);
@@ -102,7 +102,7 @@ AMDGPUDevice::readConfig(PacketPtr pkt)
Tick
AMDGPUDevice::writeConfig(PacketPtr pkt)
{
M5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
GEM5_VAR_USED int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
DPRINTF(AMDGPUDevice, "Write Config: from offset: %#x size: %#x "
"data: %#x\n", offset, pkt->getSize(),
pkt->getUintX(ByteOrder::little));

2
src/dev/arm/gic_v2.cc
View File

@@ -390,7 +390,7 @@ GicV2::writeDistributor(PacketPtr pkt)
const ContextID ctx = pkt->req->contextId();
const size_t data_sz = pkt->getSize();
M5_VAR_USED uint32_t pkt_data;
GEM5_VAR_USED uint32_t pkt_data;
switch (data_sz)
{
case 1:

6
src/dev/hsa/hsa_packet_processor.cc
View File

@@ -127,7 +127,7 @@ HSAPacketProcessor::write(Packet *pkt)
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
// TODO: How to get pid??
M5_VAR_USED Addr daddr = pkt->getAddr() - pioAddr;
GEM5_VAR_USED Addr daddr = pkt->getAddr() - pioAddr;
DPRINTF(HSAPacketProcessor,
"%s: write of size %d to reg-offset %d (0x%x)\n",
@@ -265,7 +265,7 @@ void
HSAPacketProcessor::CmdQueueCmdDmaEvent::process()
{
uint32_t rl_idx = series_ctx->rl_idx;
M5_VAR_USED AQLRingBuffer *aqlRingBuffer =
GEM5_VAR_USED AQLRingBuffer *aqlRingBuffer =
hsaPP->regdQList[rl_idx]->qCntxt.aqlBuf;
HSAQueueDescriptor* qDesc =
hsaPP->regdQList[rl_idx]->qCntxt.qDesc;
@@ -608,7 +608,7 @@ HSAPacketProcessor::getCommandsFromHost(int pid, uint32_t rl_idx)
void
HSAPacketProcessor::displayQueueDescriptor(int pid, uint32_t rl_idx)
{
M5_VAR_USED HSAQueueDescriptor* qDesc = regdQList[rl_idx]->qCntxt.qDesc;
GEM5_VAR_USED HSAQueueDescriptor* qDesc = regdQList[rl_idx]->qCntxt.qDesc;
DPRINTF(HSAPacketProcessor,
"%s: pid[%d], basePointer[0x%lx], dBPointer[0x%lx], "
"writeIndex[0x%x], readIndex[0x%x], size(bytes)[0x%x]\n",

2
src/dev/hsa/hw_scheduler.cc
View File

@@ -113,7 +113,7 @@ HWScheduler::registerNewQueue(uint64_t hostReadIndexPointer,
// Check if this newly created queue can be directly mapped
// to registered queue list
M5_VAR_USED bool register_q = mapQIfSlotAvlbl(queue_id, aql_buf, q_desc);
GEM5_VAR_USED bool register_q = mapQIfSlotAvlbl(queue_id, aql_buf, q_desc);
schedWakeup();
DPRINTF(HSAPacketProcessor,
"%s: offset = %p, qID = %d, is_regd = %s, AL size %d\n",

2
src/dev/net/sinic.cc
View File

@@ -219,7 +219,7 @@ Device::read(PacketPtr pkt)
prepareRead(cpu, index);
M5_VAR_USED uint64_t value = 0;
GEM5_VAR_USED uint64_t value = 0;
if (pkt->getSize() == 4) {
uint32_t reg = regData32(raddr);
pkt->setLE(reg);

2
src/dev/net/tcp_iface.cc
View File

@@ -251,7 +251,7 @@ TCPIface::connect()
TCPIface::~TCPIface()
{
M5_VAR_USED int ret;
GEM5_VAR_USED int ret;
ret = close(sock);
assert(ret == 0);

8
src/dev/pci/copy_engine.cc
View File

@@ -306,19 +306,19 @@ CopyEngine::write(PacketPtr pkt)
///
if (size == sizeof(uint64_t)) {
M5_VAR_USED uint64_t val = pkt->getLE<uint64_t>();
GEM5_VAR_USED uint64_t val = pkt->getLE<uint64_t>();
DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
daddr, val);
} else if (size == sizeof(uint32_t)) {
M5_VAR_USED uint32_t val = pkt->getLE<uint32_t>();
GEM5_VAR_USED uint32_t val = pkt->getLE<uint32_t>();
DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
daddr, val);
} else if (size == sizeof(uint16_t)) {
M5_VAR_USED uint16_t val = pkt->getLE<uint16_t>();
GEM5_VAR_USED uint16_t val = pkt->getLE<uint16_t>();
DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
daddr, val);
} else if (size == sizeof(uint8_t)) {
M5_VAR_USED uint8_t val = pkt->getLE<uint8_t>();
GEM5_VAR_USED uint8_t val = pkt->getLE<uint8_t>();
DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
daddr, val);
} else {

4
src/dev/virtio/pci.cc
View File

@@ -65,7 +65,7 @@ PciVirtIO::~PciVirtIO()
Tick
PciVirtIO::read(PacketPtr pkt)
{
M5_VAR_USED const unsigned size(pkt->getSize());
GEM5_VAR_USED const unsigned size(pkt->getSize());
int bar;
Addr offset;
if (!getBAR(pkt->getAddr(), bar, offset))
@@ -146,7 +146,7 @@ PciVirtIO::read(PacketPtr pkt)
Tick
PciVirtIO::write(PacketPtr pkt)
{
M5_VAR_USED const unsigned size(pkt->getSize());
GEM5_VAR_USED const unsigned size(pkt->getSize());
int bar;
Addr offset;
if (!getBAR(pkt->getAddr(), bar, offset))