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misc: Replace M5_VAR_USED with GEM5_VAR_USED.

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Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Gabe Black
2021-05-08 20:23:10 -07:00
parent e55ae090b3
commit fb3befcc6d
69 changed files with 133 additions and 132 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/minor/fetch1.cc
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@@ -390,7 +390,7 @@ void
Fetch1::minorTraceResponseLine(const std::string &name,
Fetch1::FetchRequestPtr response) const
{
M5_VAR_USED const RequestPtr &request = response->request;
GEM5_VAR_USED const RequestPtr &request = response->request;
if (response->packet && response->packet->isError()) {
MINORLINE(this, "id=F;%s vaddr=0x%x fault=\"error packet\"\n",

6
src/cpu/minor/lsq.cc
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@@ -78,7 +78,7 @@ LSQ::LSQRequest::tryToSuppressFault()
SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
TheISA::PCState old_pc = thread.pcState();
ExecContext context(port.cpu, thread, port.execute, inst, zeroReg);
M5_VAR_USED Fault fault = inst->translationFault;
GEM5_VAR_USED Fault fault = inst->translationFault;
// Give the instruction a chance to suppress a translation fault
inst->translationFault = inst->staticInst->initiateAcc(&context, nullptr);
@@ -334,7 +334,7 @@ LSQ::SplitDataRequest::finish(const Fault &fault_, const RequestPtr &request_,
{
port.numAccessesInDTLB--;
M5_VAR_USED unsigned int expected_fragment_index =
GEM5_VAR_USED unsigned int expected_fragment_index =
numTranslatedFragments;
numInTranslationFragments--;
@@ -475,7 +475,7 @@ LSQ::SplitDataRequest::makeFragmentRequests()
for (unsigned int fragment_index = 0; fragment_index < numFragments;
fragment_index++)
{
M5_VAR_USED bool is_last_fragment = false;
GEM5_VAR_USED bool is_last_fragment = false;
if (fragment_addr == base_addr) {
/* First fragment */

2
src/cpu/o3/commit_impl.hh
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@@ -707,7 +707,7 @@ DefaultCommit<Impl>::tick()
// will be active.
_nextStatus = Active;
M5_VAR_USED const DynInstPtr &inst = rob->readHeadInst(tid);
GEM5_VAR_USED const DynInstPtr &inst = rob->readHeadInst(tid);
DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of"
" ROB and ready to commit\n",

2
src/cpu/o3/lsq_impl.hh
View File

@@ -683,7 +683,7 @@ LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
// This comming request can be either load, store or atomic.
// Atomic request has a corresponding pointer to its atomic memory
// operation
M5_VAR_USED bool isAtomic = !isLoad && amo_op;
GEM5_VAR_USED bool isAtomic = !isLoad && amo_op;
ThreadID tid = cpu->contextToThread(inst->contextId());
auto cacheLineSize = cpu->cacheLineSize();

2
src/cpu/o3/mem_dep_unit_impl.hh
View File

@@ -270,7 +270,7 @@ MemDepUnit<MemDepPred, Impl>::insert(const DynInstPtr &inst)
} else {
// Otherwise make the instruction dependent on the store/barrier.
DPRINTF(MemDepUnit, "Adding to dependency list\n");
for (M5_VAR_USED auto producing_store : producing_stores)
for (GEM5_VAR_USED auto producing_store : producing_stores)
DPRINTF(MemDepUnit, "\tinst PC %s is dependent on [sn:%lli].\n",
inst->pcState(), producing_store);

2
src/cpu/pred/bpred_unit.cc
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@@ -111,7 +111,7 @@ BPredUnit::drainSanityCheck() const
{
// We shouldn't have any outstanding requests when we resume from
// a drained system.
for (M5_VAR_USED const auto& ph : predHist)
for (GEM5_VAR_USED const auto& ph : predHist)
assert(ph.empty());
}

4
src/cpu/simple/timing.cc
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@@ -166,7 +166,7 @@ void
TimingSimpleCPU::switchOut()
{
SimpleExecContext& t_info = *threadInfo[curThread];
M5_VAR_USED SimpleThread* thread = t_info.thread;
GEM5_VAR_USED SimpleThread* thread = t_info.thread;
// hardware transactional memory
// Cannot switch out the CPU in the middle of a transaction
@@ -937,7 +937,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
// hardware transactional memory
SimpleExecContext *t_info = threadInfo[curThread];
M5_VAR_USED const bool is_htm_speculative =
GEM5_VAR_USED const bool is_htm_speculative =
t_info->inHtmTransactionalState();
// received a response from the dcache: complete the load or store

2
src/cpu/testers/memtest/memtest.cc
View File

@@ -243,7 +243,7 @@ MemTest::tick()
if (cmd < percentReads) {
// start by ensuring there is a reference value if we have not
// seen this address before
M5_VAR_USED uint8_t ref_data = 0;
GEM5_VAR_USED uint8_t ref_data = 0;
auto ref = referenceData.find(req->getPaddr());
if (ref == referenceData.end()) {
referenceData[req->getPaddr()] = 0;

4
src/cpu/trace/trace_cpu.cc
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@@ -811,7 +811,7 @@ TraceCPU::ElasticDataGen::printReadyList()
DPRINTF(TraceCPUData, "Printing readyList:\n");
while (itr != readyList.end()) {
auto graph_itr = depGraph.find(itr->seqNum);
M5_VAR_USED GraphNode* node_ptr = graph_itr->second;
GEM5_VAR_USED GraphNode* node_ptr = graph_itr->second;
DPRINTFR(TraceCPUData, "\t%lld(%s), %lld\n", itr->seqNum,
node_ptr->typeToStr(), itr->execTick);
itr++;
@@ -1322,7 +1322,7 @@ TraceCPU::ElasticDataGen::GraphNode::removeDepOnInst(NodeSeqNum done_seq_num)
// If it is not an rob dependency then it must be a register dependency
// If the register dependency is not found, it violates an assumption
// and must be caught by assert.
M5_VAR_USED bool regdep_found = removeRegDep(done_seq_num);
GEM5_VAR_USED bool regdep_found = removeRegDep(done_seq_num);
assert(regdep_found);
}
// Return true if the node is dependency free