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misc: Replace M5_VAR_USED with GEM5_VAR_USED.

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Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Gabe Black
2021-05-08 20:23:10 -07:00
parent e55ae090b3
commit fb3befcc6d
69 changed files with 133 additions and 132 deletions
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4
src/arch/mips/interrupts.cc
View File

@@ -145,8 +145,8 @@ Interrupts::getInterrupt()
{
assert(checkInterrupts());
M5_VAR_USED StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
M5_VAR_USED CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
GEM5_VAR_USED StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
GEM5_VAR_USED CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
(unsigned)status.im, (unsigned)cause.ip);

2
src/arch/mips/isa/formats/mem.isa
View File

@@ -407,7 +407,7 @@ def template MiscExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
M5_VAR_USED Addr EA = 0;
GEM5_VAR_USED Addr EA = 0;
Fault fault = NoFault;
%(fp_enable_check)s;

2
src/arch/mips/isa/formats/mt.isa
View File

@@ -111,7 +111,7 @@ def template ThreadRegisterExecute {{
ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
M5_VAR_USED int64_t data;
GEM5_VAR_USED int64_t data;
%(op_decl)s;
%(op_rd)s;