derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

misc: Replace M5_VAR_USED with GEM5_VAR_USED.

Browse Source 
Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Gabe Black
2021-05-08 20:23:10 -07:00
parent e55ae090b3
commit fb3befcc6d
69 changed files with 133 additions and 132 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/arch/arm/faults.cc
View File

@@ -517,7 +517,7 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
saved_cpsr.v = tc->readCCReg(CCREG_V);
saved_cpsr.ge = tc->readCCReg(CCREG_GE);
M5_VAR_USED Addr curPc = tc->pcState().pc();
GEM5_VAR_USED Addr curPc = tc->pcState().pc();
ITSTATE it = tc->pcState().itstate();
saved_cpsr.it2 = it.top6;
saved_cpsr.it1 = it.bottom2;
@@ -525,7 +525,7 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
// if we have a valid instruction then use it to annotate this fault with
// extra information. This is used to generate the correct fault syndrome
// information
M5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst);
GEM5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst);
// Ensure Secure state if initially in Monitor mode
if (have_security && saved_cpsr.mode == MODE_MON) {
@@ -703,7 +703,7 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
// If we have a valid instruction then use it to annotate this fault with
// extra information. This is used to generate the correct fault syndrome
// information
M5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst);
GEM5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst);
// Set PC to start of exception handler
Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL, true);
@@ -755,7 +755,7 @@ Reset::getVector(ThreadContext *tc)
Addr base;
// Check for invalid modes
M5_VAR_USED CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
GEM5_VAR_USED CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
@@ -1069,7 +1069,7 @@ AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
// See ARM ARM B3-1416
bool override_LPAE = false;
TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
M5_VAR_USED TTBCR ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
GEM5_VAR_USED TTBCR ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
if (ttbcr_s.eae) {
override_LPAE = true;
} else {

4
src/arch/arm/insts/macromem.cc
View File

@@ -560,7 +560,7 @@ VldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst,
unsigned eBytes = (1 << size);
unsigned loadSize = eBytes * elems;
M5_VAR_USED unsigned loadRegs =
GEM5_VAR_USED unsigned loadRegs =
(loadSize + sizeof(uint32_t) - 1) / sizeof(uint32_t);
assert(loadRegs > 0 && loadRegs <= 4);
@@ -924,7 +924,7 @@ VstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst,
unsigned eBytes = (1 << size);
unsigned storeSize = eBytes * elems;
M5_VAR_USED unsigned storeRegs =
GEM5_VAR_USED unsigned storeRegs =
(storeSize + sizeof(uint32_t) - 1) / sizeof(uint32_t);
assert(storeRegs > 0 && storeRegs <= 4);

12
src/arch/arm/isa/insts/data64.isa
View File

@@ -83,16 +83,16 @@ let {{
"logic": '0'
}
immOp2 = "M5_VAR_USED uint64_t secOp = imm;"
sRegOp2 = "M5_VAR_USED uint64_t secOp = " + \
immOp2 = "GEM5_VAR_USED uint64_t secOp = imm;"
sRegOp2 = "GEM5_VAR_USED uint64_t secOp = " + \
"shiftReg64(Op264, shiftAmt, shiftType, intWidth);"
eRegOp2 = "M5_VAR_USED uint64_t secOp = " + \
eRegOp2 = "GEM5_VAR_USED uint64_t secOp = " + \
"extendReg64(Op264, extendType, shiftAmt, intWidth);"
def buildDataWork(mnem, code, flagType, suffix, buildCc, buildNonCc,
base, templateBase):
code = '''
M5_VAR_USED uint64_t resTemp = 0;
GEM5_VAR_USED uint64_t resTemp = 0;
''' + code
ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType])
Name = mnem.capitalize() + suffix
@@ -577,9 +577,9 @@ let {{
def condCompCode(flagType, op, imm):
ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType])
opDecl = "M5_VAR_USED uint64_t secOp = imm;"
opDecl = "GEM5_VAR_USED uint64_t secOp = imm;"
if not imm:
opDecl = "M5_VAR_USED uint64_t secOp = Op264;"
opDecl = "GEM5_VAR_USED uint64_t secOp = Op264;"
return opDecl + '''
if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)) {
uint64_t resTemp = Op164 ''' + op + ''' secOp;

4
src/arch/arm/isa/insts/fp.isa
View File

@@ -467,7 +467,7 @@ let {{
exec_output = ""
singleSimpleCode = vfpEnabledCheckCode + '''
M5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc;
GEM5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc;
FpDest = %(op)s;
'''
singleCode = singleSimpleCode + '''
@@ -488,7 +488,7 @@ let {{
"%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)"
singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
doubleCode = vfpEnabledCheckCode + '''
M5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc;
GEM5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc;
double dest = %(op)s;
FpDestP0_uw = dblLow(dest);
FpDestP1_uw = dblHi(dest);

2
src/arch/arm/isa/insts/ldr64.isa
View File

@@ -201,7 +201,7 @@ let {{
accEpilogCode = None
# Code that actually handles the access
if self.flavor in ("dprefetch", "iprefetch", "mprefetch"):
accCode = 'M5_VAR_USED uint64_t temp = Mem%s;'
accCode = 'GEM5_VAR_USED uint64_t temp = Mem%s;'
elif self.flavor == "fp":
accEpilogCode = '''
ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,

2
src/arch/arm/isa/insts/misc64.isa
View File

@@ -128,7 +128,7 @@ let {{
bitMask = (bitMask >> imm1) | (bitMask << (intWidth - imm1));
diff += intWidth;
}
M5_VAR_USED uint64_t topBits = ~mask(diff+1);
GEM5_VAR_USED uint64_t topBits = ~mask(diff+1);
uint64_t result = imm1 == 0 ? Op164 :
(Op164 >> imm1) | (Op164 << (intWidth - imm1));
result &= bitMask;

6
src/arch/arm/isa/insts/sve.isa
View File

@@ -2007,7 +2007,7 @@ let {{
destPred.reset();
for (unsigned i = 0; i < eCount; i++) {
const Element& srcElem1 = AA64FpOp1_x[i];
M5_VAR_USED %(src_elem_2_ty)s srcElem2 = %(src_elem_2)s;
GEM5_VAR_USED %(src_elem_2_ty)s srcElem2 = %(src_elem_2)s;
bool destElem = false;
if (tmpPred[i]) {
%(op)s
@@ -2703,7 +2703,7 @@ let {{
CondCodesC = !destPred.lastActive(GpOp, eCount);
CondCodesV = 0;'''
extraPrologCode = '''
M5_VAR_USED auto& destPred = PDest;'''
GEM5_VAR_USED auto& destPred = PDest;'''
baseClass = ('SvePredUnaryWImplicitSrcOp' if predType == PredType.NONE
else 'SvePredUnaryWImplicitSrcPredOp')
iop = ArmInstObjParams(name, 'Sve' + Name, baseClass,
@@ -2722,7 +2722,7 @@ let {{
global header_output, exec_output, decoders
code = sveEnabledCheckCode + op
extraPrologCode = '''
M5_VAR_USED auto& destPred = Ffr;'''
GEM5_VAR_USED auto& destPred = Ffr;'''
baseClass = ('SveWImplicitSrcDstOp' if isSetFfr
else 'SvePredUnaryWImplicitDstOp')
iop = ArmInstObjParams(name, 'Sve' + Name, baseClass,

4
src/arch/arm/isa/templates/mem.isa
View File

@@ -1164,7 +1164,7 @@ def template LoadRegConstructor {{
{
%(set_reg_idx_arr)s;
%(constructor)s;
M5_VAR_USED bool conditional = false;
GEM5_VAR_USED bool conditional = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
@@ -1231,7 +1231,7 @@ def template LoadImmConstructor {{
{
%(set_reg_idx_arr)s;
%(constructor)s;
M5_VAR_USED bool conditional = false;
GEM5_VAR_USED bool conditional = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {

38
src/arch/arm/isa/templates/sve_mem.isa
View File

@@ -157,7 +157,7 @@ def template SveContigLoadExecute {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<RegElemType>(xc->tcBase());
@@ -192,7 +192,7 @@ def template SveContigLoadInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<RegElemType>(xc->tcBase());
@@ -217,7 +217,7 @@ def template SveContigLoadCompleteAcc {{
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
{
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<RegElemType>(xc->tcBase());
@@ -247,7 +247,7 @@ def template SveContigStoreExecute {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<RegElemType>(xc->tcBase());
@@ -285,7 +285,7 @@ def template SveContigStoreInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<RegElemType>(xc->tcBase());
@@ -329,7 +329,7 @@ def template SveLoadAndReplExecute {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<RegElemType>(xc->tcBase());
@@ -361,7 +361,7 @@ def template SveLoadAndReplInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
%(op_src_decl)s;
%(op_rd)s;
@@ -386,7 +386,7 @@ def template SveLoadAndReplCompleteAcc {{
ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<RegElemType>(xc->tcBase());
@@ -585,7 +585,7 @@ def template SveGatherLoadMicroopExecute {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -634,7 +634,7 @@ def template SveGatherLoadMicroopInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
%(op_src_decl)s;
%(op_rd)s;
@@ -675,7 +675,7 @@ def template SveGatherLoadMicroopCompleteAcc {{
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
{
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -702,7 +702,7 @@ def template SveScatterStoreMicroopExecute {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -733,7 +733,7 @@ def template SveScatterStoreMicroopInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -806,7 +806,7 @@ def template SveFirstFaultWritebackMicroopExecute {{
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -989,7 +989,7 @@ def template SveStructLoadExecute {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<Element>(xc->tcBase());
@@ -1023,7 +1023,7 @@ def template SveStructLoadInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<Element>(xc->tcBase());
@@ -1049,7 +1049,7 @@ def template SveStructLoadCompleteAcc {{
ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<Element>(xc->tcBase());
@@ -1082,7 +1082,7 @@ def template SveStructStoreExecute {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<Element>(xc->tcBase());
@@ -1120,7 +1120,7 @@ def template SveStructStoreInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
M5_VAR_USED bool aarch64 = true;
GEM5_VAR_USED bool aarch64 = true;
unsigned eCount =
ArmStaticInst::getCurSveVecLen<Element>(xc->tcBase());

2
src/arch/arm/tlb.cc
View File

@@ -814,7 +814,7 @@ TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
// Cache clean operations require read permissions to the specified VA
bool is_write = !req->isCacheClean() && mode == Write;
bool is_atomic = req->isAtomic();
M5_VAR_USED bool is_priv = isPriv && !(flags & UserMode);
GEM5_VAR_USED bool is_priv = isPriv && !(flags & UserMode);
updateMiscReg(tc, curTranType);

2
src/arch/isa_parser/isa_parser.py
View File

@@ -133,7 +133,7 @@ class Template(object):
if operands.predRead:
myDict['op_decl'] += 'uint8_t _sourceIndex = 0;\n'
if operands.predWrite:
myDict['op_decl'] += 'M5_VAR_USED uint8_t _destIndex = 0;\n'
myDict['op_decl'] += 'GEM5_VAR_USED uint8_t _destIndex = 0;\n'
is_src = lambda op: op.is_src
is_dest = lambda op: op.is_dest

4
src/arch/mips/interrupts.cc
View File

@@ -145,8 +145,8 @@ Interrupts::getInterrupt()
{
assert(checkInterrupts());
M5_VAR_USED StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
M5_VAR_USED CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
GEM5_VAR_USED StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
GEM5_VAR_USED CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
(unsigned)status.im, (unsigned)cause.ip);

2
src/arch/mips/isa/formats/mem.isa
View File

@@ -407,7 +407,7 @@ def template MiscExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
M5_VAR_USED Addr EA = 0;
GEM5_VAR_USED Addr EA = 0;
Fault fault = NoFault;
%(fp_enable_check)s;

2
src/arch/mips/isa/formats/mt.isa
View File

@@ -111,7 +111,7 @@ def template ThreadRegisterExecute {{
ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
M5_VAR_USED int64_t data;
GEM5_VAR_USED int64_t data;
%(op_decl)s;
%(op_rd)s;

2
src/arch/power/isa/formats/mem.isa
View File

@@ -112,7 +112,7 @@ def template LoadCompleteAcc {{
ExecContext *xc,
Trace::InstRecord *traceData) const
{
M5_VAR_USED Addr EA;
GEM5_VAR_USED Addr EA;
Fault fault = NoFault;
%(op_decl)s;

2
src/arch/riscv/isa.cc
View File

@@ -53,7 +53,7 @@
namespace RiscvISA
{
M5_VAR_USED const std::array<const char *, NUM_MISCREGS> MiscRegNames = {{
GEM5_VAR_USED const std::array<const char *, NUM_MISCREGS> MiscRegNames = {{
[MISCREG_PRV] = "PRV",
[MISCREG_ISA] = "ISA",
[MISCREG_VENDORID] = "VENDORID",

2
src/arch/sparc/faults.cc
View File

@@ -813,7 +813,7 @@ TrapInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
Process *p = tc->getProcessPtr();
M5_VAR_USED SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
GEM5_VAR_USED SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
assert(sp);
auto *workload = dynamic_cast<SEWorkload *>(tc->getSystemPtr()->workload);

2
src/arch/x86/isa/microops/base.isa
View File

@@ -213,7 +213,7 @@ let {{
Macroop * macroop = dynamic_cast<Macroop *>(curMacroop.get());
const ExtMachInst &machInst =
macroop ? macroop->getExtMachInst() : dummyExtMachInst;
M5_VAR_USED const EmulEnv &env =
GEM5_VAR_USED const EmulEnv &env =
macroop ? macroop->getEmulEnv() : dummyEmulEnv;
using namespace RomLabels;
return %s;

2
src/arch/x86/isa/microops/regop.isa
View File

@@ -50,7 +50,7 @@ def template MicroRegOpExecute {{
%(op_decl)s;
%(op_rd)s;
M5_VAR_USED RegVal result;
GEM5_VAR_USED RegVal result;
if (%(cond_check)s) {
%(code)s;

2
src/arch/x86/ldstflags.hh
View File

@@ -46,7 +46,7 @@
*/
namespace X86ISA
{
M5_VAR_USED const Request::FlagsType SegmentFlagMask = mask(4);
GEM5_VAR_USED const Request::FlagsType SegmentFlagMask = mask(4);
const int FlagShift = 4;
enum FlagBit
{