SPARC: Phase out SPARC's intregfile.hh.

src/arch/sparc/interrupts.hh

@@ -34,6 +34,7 @@
 
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregfile.hh"
 #include "cpu/thread_context.hh"
 #include "params/SparcInterrupts.hh"
 #include "sim/sim_object.hh"

src/arch/sparc/intregfile.hh

@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Ali Saidi
- */
-
-#ifndef __ARCH_SPARC_INTREGFILE_HH__
-#define __ARCH_SPARC_INTREGFILE_HH__
-
-#include "arch/sparc/sparc_traits.hh"
-
-namespace SparcISA
-{
-    const int NumIntArchRegs = 32;
-    const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
-}
-
-#endif

src/arch/sparc/predecoder.hh

@@ -31,6 +31,7 @@
 #ifndef __ARCH_SPARC_PREDECODER_HH__
 #define __ARCH_SPARC_PREDECODER_HH__
 
+#include "arch/sparc/miscregfile.hh"
 #include "arch/sparc/types.hh"
 #include "base/bitfield.hh"
 #include "base/misc.hh"

src/arch/sparc/process.cc

@@ -32,6 +32,7 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/handlers.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregfile.hh"
 #include "arch/sparc/process.hh"
 #include "arch/sparc/types.hh"
 #include "base/loader/object_file.hh"

src/arch/sparc/regfile.cc

@@ -30,6 +30,7 @@
  */
 
 #include "arch/sparc/regfile.hh"
+#include "arch/sparc/miscregfile.hh"
 #include "cpu/thread_context.hh"
 
 class Checkpoint;

src/arch/sparc/regfile.hh

@@ -34,16 +34,20 @@
 
 #include <string>
 
-#include "arch/sparc/intregfile.hh"
-#include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/miscregfile.hh"
-#include "arch/sparc/types.hh"
+#include "arch/sparc/sparc_traits.hh"
 #include "base/types.hh"
+#include "sim/serialize.hh"
 
 class Checkpoint;
+class EventManager;
+class ThreadContext;
 
 namespace SparcISA
 {
+    const int NumIntArchRegs = 32;
+    const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
+
     class RegFile
     {
       protected:

src/arch/sparc/utility.hh

@@ -33,6 +33,7 @@
 
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregfile.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/misc.hh"
 #include "base/bitfield.hh"