stdlib: Clean up Ruby cache directory

- Fix typos.
- Fix type inconsistencies.

Change-Id: I98d82ec7e62130abb09295c5ec6cde86b1f7fa27
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65571
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py

@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-# from .abstract_cache_hierarchy import AbstractCacheHierarchy
-
 
 class AbstractTwoLevelCacheHierarchy:
     """
@@ -51,9 +49,9 @@ class AbstractTwoLevelCacheHierarchy:
 
         :type l1i_assoc: int
 
-        :param l1dsize: The size of the LL1 Data cache (e.g. "32kB").
+        :param l1d_size: The size of the L1 Data cache (e.g. "32kB").
 
-        :type l1dsize: str
+        :type l1d_size: str
 
         :param l1d_assoc:
 

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py

@@ -45,7 +45,7 @@ class L2Cache(AbstractL2Cache):
             start_index_bit=self.getIndexBit(num_l2Caches),
         )
 
-        self.transitions_per_cycle = "4"
+        self.transitions_per_cycle = 4
 
     def getIndexBit(self, num_l2caches):
         l2_bits = int(math.log(num_l2caches, 2))