From f99947059d4bd22cf066f5261b10be4e8e333fc5 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Sat, 12 Nov 2022 08:00:49 +0000 Subject: [PATCH] stdlib: Clean up Ruby cache directory - Fix typos. - Fix type inconsistencies. Change-Id: I98d82ec7e62130abb09295c5ec6cde86b1f7fa27 Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65571 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- .../cachehierarchies/abstract_two_level_cache_hierarchy.py | 6 ++---- .../cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py index 17cae4aba8..d6a035f2cb 100644 --- a/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py @@ -24,8 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# from .abstract_cache_hierarchy import AbstractCacheHierarchy - class AbstractTwoLevelCacheHierarchy: """ @@ -51,9 +49,9 @@ class AbstractTwoLevelCacheHierarchy: :type l1i_assoc: int - :param l1dsize: The size of the LL1 Data cache (e.g. "32kB"). + :param l1d_size: The size of the L1 Data cache (e.g. "32kB"). - :type l1dsize: str + :type l1d_size: str :param l1d_assoc: diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py index 56cb5b2ec1..81ef4dbe90 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py @@ -45,7 +45,7 @@ class L2Cache(AbstractL2Cache): start_index_bit=self.getIndexBit(num_l2Caches), ) - self.transitions_per_cycle = "4" + self.transitions_per_cycle = 4 def getIndexBit(self, num_l2caches): l2_bits = int(math.log(num_l2caches, 2))