x86: Switch from MessageReq and Resp to WriteReq and Resp.

Originally MessageReq was intended to mark a packet as a holding a
message destined for a particular recipient and which would not
interact with other packets.

This is similar to the way a WriteReq would behave if writing to a
device register which needs to be updated atomically. Also, while the
memory system *could* recognize a MessageReq and know that it didn't
need to interact with other packets, that was never implemented.

Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

src/dev/x86/intdev.hh

@@ -76,7 +76,7 @@ class IntSlavePort : public SimpleTimingPort
     Tick
     recvAtomic(PacketPtr pkt)
     {
-        panic_if(pkt->cmd != MemCmd::MessageReq,
+        panic_if(pkt->cmd != MemCmd::WriteReq,
                 "%s received unexpected command %s from %s.\n",
                 name(), pkt->cmd.toString(), getPeer());
         pkt->headerDelay = pkt->payloadDelay = 0;