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arch-x86: Change warn to warn_once for NT instructions

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Change-Id: I50353716f2a913b9b106b140644d95991879f662
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Hoa Nguyen
2019-09-18 16:50:19 -07:00
parent 2455f6c0dd
commit f85cdccf41
2 changed files with 4 additions and 4 deletions
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4
src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py
View File

@@ -38,14 +38,14 @@
microcode = '''
def macroop MOVNTDQ_M_XMM {
warn "MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!"
warn_once "MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!"
cda seg, sib, "DISPLACEMENT + 8", dataSize=8
stfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
};
def macroop MOVNTDQ_P_XMM {
warn "MOVNTDQ_P: Ignoring non-temporal hint, modeling as cacheable!"
warn_once "MOVNTDQ_P: Ignoring non-temporal hint, modeling as cacheable!"
rdip t7
cda seg, riprel, "DISPLACEMENT + 8", dataSize=8
stfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8

4
src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py
View File

@@ -38,12 +38,12 @@
microcode = '''
def macroop MOVNTQ_M_MMX {
warn "MOVNTQ: Ignoring non-temporal hint, modeling as cacheable!"
warn_once "MOVNTQ: Ignoring non-temporal hint, modeling as cacheable!"
stfp mmx, seg, sib, "DISPLACEMENT", dataSize=8
};
def macroop MOVNTQ_P_MMX {
warn "MOVNTQ_P: Ignoring non-temporal hint, modeling as cacheable!"
warn_once "MOVNTQ_P: Ignoring non-temporal hint, modeling as cacheable!"
rdip t7
stfp mmx, seg, riprel, "DISPLACEMENT", dataSize=8
};