derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-riscv: Initial the privilege modes configuration

Browse Source 
1. Declare the new enum type PrivilegeModes
2. Disallow setting the MISA register RVU and RVS.

Change-Id: I932d714bc70c9720a706353c557a5be76c950f81
This commit is contained in:
Roger Chang
2023-10-30 10:37:56 +08:00
parent d94d6017b0
commit f745e8cf89
5 changed files with 51 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/riscv/SConscript
View File

@@ -73,7 +73,7 @@ SimObject('RiscvFsWorkload.py',
SimObject('RiscvInterrupts.py', sim_objects=['RiscvInterrupts'],
tags='riscv isa')
SimObject('RiscvISA.py', sim_objects=['RiscvISA'],
enums=['RiscvType'], tags='riscv isa')
enums=['RiscvType', 'PrivilegeModeSet'], tags='riscv isa')
SimObject('RiscvMMU.py', sim_objects=['RiscvMMU'], tags='riscv isa')
SimObject('RiscvSeWorkload.py', sim_objects=[
'RiscvSEWorkload', 'RiscvEmuLinux'], tags='riscv isa')