From f745e8cf89e31abe7957109cc8ae02eb634b025e Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Mon, 30 Oct 2023 10:37:56 +0800
Subject: [PATCH] arch-riscv: Initial the privilege modes configuration

1. Declare the new enum type PrivilegeModes
2. Disallow setting the MISA register RVU and RVS.

Change-Id: I932d714bc70c9720a706353c557a5be76c950f81
---
 src/arch/riscv/RiscvISA.py | 15 +++++++++++++++
 src/arch/riscv/SConscript  |  2 +-
 src/arch/riscv/isa.cc      | 29 +++++++++++++++++++++++++----
 src/arch/riscv/isa.hh      |  7 +++++++
 src/arch/riscv/pcstate.hh  |  3 +++
 5 files changed, 51 insertions(+), 5 deletions(-)

diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py
index bce7f2497f..5d53c882aa 100644
--- a/src/arch/riscv/RiscvISA.py
+++ b/src/arch/riscv/RiscvISA.py
@@ -74,6 +74,16 @@ class RiscvType(Enum):
     vals = ["RV32", "RV64"]
 
 
+class PrivilegeModeSet(Enum):
+    vals = [
+        "M",  # Machine privilege mode only
+        "MU",  # Machine and user privlege modes implemented
+        "MNU",  # MU privilege modes with user-mode trap
+        "MSU",  # Machine, supervisor and user modes implemented
+        "MNSU",  # MSU privilege modes with user-mode trap
+    ]
+
+
 class RiscvISA(BaseISA):
     type = "RiscvISA"
     cxx_class = "gem5::RiscvISA::ISA"
@@ -95,6 +105,11 @@ class RiscvISA(BaseISA):
         "Length of each vector element in bits. \
         ELEN in Ch. 2 of RISC-V vector spec",
     )
+    privilege_mode_set = Param.PrivilegeModeSet(
+        "MSU",
+        "The combination of privilege modes \
+        in Privilege Levels section of RISC-V privileged spec",
+    )
 
     enable_Zicbom_fs = Param.Bool(True, "Enable Zicbom extension in FS mode")
     enable_Zicboz_fs = Param.Bool(True, "Enable Zicboz extension in FS mode")
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index d3dd1d5970..41da97bcc1 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -73,7 +73,7 @@ SimObject('RiscvFsWorkload.py',
 SimObject('RiscvInterrupts.py', sim_objects=['RiscvInterrupts'],
     tags='riscv isa')
 SimObject('RiscvISA.py', sim_objects=['RiscvISA'],
-    enums=['RiscvType'], tags='riscv isa')
+    enums=['RiscvType', 'PrivilegeModeSet'], tags='riscv isa')
 SimObject('RiscvMMU.py', sim_objects=['RiscvMMU'], tags='riscv isa')
 SimObject('RiscvSeWorkload.py', sim_objects=[
     'RiscvSEWorkload', 'RiscvEmuLinux'], tags='riscv isa')
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 0ba6d15b6c..81fb7f3061 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -254,9 +254,10 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
 
 } // anonymous namespace
 
-ISA::ISA(const Params &p) :BaseISA(p),
+ISA::ISA(const Params &p) : BaseISA(p),
     _rvType(p.riscv_type), checkAlignment(p.check_alignment),
-    enableRvv(p.enable_rvv),vlen(p.vlen),elen(p.elen)
+    enableRvv(p.enable_rvv), vlen(p.vlen), elen(p.elen),
+    _privilegeModeSet(p.privilege_mode_set)
 {
     _regClasses.push_back(&intRegClass);
     _regClasses.push_back(&floatRegClass);
@@ -324,8 +325,25 @@ void ISA::clear()
 
     // default config arch isa string is rv64(32)imafdc
     misa.rvi = misa.rvm = misa.rva = misa.rvf = misa.rvd = misa.rvc = 1;
-    // default privlege modes if MSU
-    misa.rvs = misa.rvu = 1;
+
+    switch (getPrivilegeModeSet()) {
+        case enums::M:
+          break;
+        case enums::MU:
+          misa.rvu = 1;
+          break;
+        case enums::MNU:
+          misa.rvu = misa.rvn = 1;
+          break;
+        case enums::MSU:
+          misa.rvs = misa.rvu = 1;
+          break;
+        case enums::MNSU:
+          misa.rvs = misa.rvu = misa.rvn = 1;
+          break;
+        default:
+          panic("Privilege mode set config should not reach here");
+    }
 
     // mark FS is initial
     status.fs = INITIAL;
@@ -697,6 +715,9 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                 if (!getEnableRvv()) {
                     new_misa.rvv = 0;
                 }
+                new_misa.rvn = cur_misa.rvn;
+                new_misa.rvs = cur_misa.rvs;
+                new_misa.rvu = cur_misa.rvu;
                 setMiscRegNoEffect(idx, new_misa);
             }
             break;
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 66cba0f7fa..6a3547ab2c 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -94,6 +94,11 @@ class ISA : public BaseISA
     */
     unsigned elen;
 
+    /** The combination of privilege modes
+     *  in Privilege Levels section of RISC-V privileged spec
+     */
+    PrivilegeModeSet _privilegeModeSet;
+
   public:
     using Params = RiscvISAParams;
 
@@ -164,6 +169,8 @@ class ISA : public BaseISA
     unsigned getVecLenInBytes() { return vlen >> 3; }
     unsigned getVecElemLenInBits() { return elen; }
 
+    PrivilegeModeSet getPrivilegeModeSet() { return _privilegeModeSet; }
+
     virtual Addr getFaultHandlerAddr(
         RegIndex idx, uint64_t cause, bool intr) const;
 };
diff --git a/src/arch/riscv/pcstate.hh b/src/arch/riscv/pcstate.hh
index 91fb507034..62ecd9f960 100644
--- a/src/arch/riscv/pcstate.hh
+++ b/src/arch/riscv/pcstate.hh
@@ -44,6 +44,7 @@
 
 #include "arch/generic/pcstate.hh"
 #include "arch/riscv/regs/vector.hh"
+#include "enums/PrivilegeModeSet.hh"
 #include "enums/RiscvType.hh"
 
 namespace gem5
@@ -55,6 +56,8 @@ using RiscvType = enums::RiscvType;
 constexpr enums::RiscvType RV32 = enums::RV32;
 constexpr enums::RiscvType RV64 = enums::RV64;
 
+using PrivilegeModeSet = enums::PrivilegeModeSet;
+
 class PCState : public GenericISA::UPCState<4>
 {
   protected: