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arch-arm: This commit fix incorrect ARM isa implementation

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When running 500.perlbench_r of specint 2017, the system will raise an
 assertion error. For function bits of src/base/bitfield.hh (line 76),
 the parameter First is smaller than Last. This is caused by incorrect
 implementation of uqrshl in src/arch/arm/isa/insts/neon64.isa

When shiftAmt equals 0, which mean uqrshl is actually not shift the
 value stored in register. sizeof(Element) * 8 - 1 will be smaller than
 sizeof(Element) * 8 - shiftAmt, thus will raise the assertion error.

This commit added this special condition.

No Jira issue has been submitted to report this error

Change-Id: I4162ac3ddb62f162619db400f214f33209b23c19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69318
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Marco Chen
2023-03-28 07:57:35 -07:00
parent 91637af3dc
commit f4d8fe2595
1 changed files with 3 additions and 2 deletions
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5
src/arch/arm/isa/insts/neon64.isa
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@@ -3255,8 +3255,9 @@ let {{
destElem = 0;
}
} else {
if (bits(srcElem1, sizeof(Element) * 8 - 1,
sizeof(Element) * 8 - shiftAmt)) {
if (shiftAmt != 0 &&
bits(srcElem1, sizeof(Element) * 8 - 1,
sizeof(Element) * 8 - shiftAmt)) {
destElem = mask(sizeof(Element) * 8);
fpscr.qc = 1;
} else {