fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.

This was to support port proxies and getInstPort and getDataPort. With
some recent upstream changes, getInstPort and getDataPort are only used
for CPU switching which we can't support (TLM ports are bound
permanently), and with the sendFunctional delegate for port proxies,
we don't need to have a traditional gem5 port lying around.

This gets rid of the "mem" port and all its plumbing.

Change-Id: Ic68a40a26b24aa05b33da0510c9f4b7621cbf578
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21048
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2019-08-28 17:12:55 -07:00
parent fc63dc6221
commit f469ee610f
3 changed files with 1 additions and 38 deletions

View File

@@ -36,5 +36,3 @@ class FastModelArmCPU(IrisArmCPU):
cxx_header = 'arch/arm/fastmodel/arm/cpu.hh'
cntfrq = Param.UInt64("Value for the CNTFRQ timer register")
mem = RequestPort('Port for port proxies to attach to.')

View File

@@ -35,8 +35,7 @@ namespace FastModel
{
ArmCPU::ArmCPU(FastModelArmCPUParams *params) :
Iris::ArmCPU(params, scx::scx_get_iris_connection_interface()),
mem(name() + ".mem", this)
Iris::ArmCPU(params, scx::scx_get_iris_connection_interface())
{
}
@@ -48,14 +47,6 @@ ArmCPU::initState()
tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, cntfrq);
}
Port &
ArmCPU::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "mem")
return mem;
return Iris::ArmCPU::getPort(if_name, idx);
}
} // namespace FastModel
FastModel::ArmCPU *

View File

@@ -39,36 +39,10 @@ namespace FastModel
// This class adds non-Iris, gem5 functionality to this CPU model.
class ArmCPU : public Iris::ArmCPU
{
private:
class MemPort : public MasterPort
{
public:
using MasterPort::MasterPort;
bool
recvTimingResp(PacketPtr pkt) override
{
panic("%s.%s not implemented.\n", name(), __FUNCTION__);
}
void
recvReqRetry() override
{
panic("%s.%s not implemented.\n", name(), __FUNCTION__);
}
};
MemPort mem;
public:
ArmCPU(FastModelArmCPUParams *params);
void initState() override;
Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override;
Port &getDataPort() override { return mem; }
Port &getInstPort() override { return mem; }
};
} // namespace FastModel