sparc: Passify a new g++ warning.
g++ seems to think there are some missing brackets when initializing the sparc fault information. Passify it by adding extra brackets. Change-Id: I826995f88b8ac8a21721c949a244dec480831b80 Reviewed-on: https://gem5-review.googlesource.com/8763 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
@@ -52,226 +52,226 @@ namespace SparcISA
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template<> SparcFaultBase::FaultVals
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SparcFault<PowerOnReset>::vals
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("power_on_reset", 0x001, 0, {H, H, H});
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("power_on_reset", 0x001, 0, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<WatchDogReset>::vals
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("watch_dog_reset", 0x002, 120, {H, H, H});
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("watch_dog_reset", 0x002, 120, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<ExternallyInitiatedReset>::vals
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("externally_initiated_reset", 0x003, 110, {H, H, H});
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("externally_initiated_reset", 0x003, 110, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<SoftwareInitiatedReset>::vals
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("software_initiated_reset", 0x004, 130, {SH, SH, H});
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("software_initiated_reset", 0x004, 130, {{SH, SH, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<REDStateException>::vals
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("RED_state_exception", 0x005, 1, {H, H, H});
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("RED_state_exception", 0x005, 1, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<StoreError>::vals
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("store_error", 0x007, 201, {H, H, H});
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("store_error", 0x007, 201, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionAccessException>::vals
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("instruction_access_exception", 0x008, 300, {H, H, H});
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("instruction_access_exception", 0x008, 300, {{H, H, H}});
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<InstructionAccessMMUMiss>::vals
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{"inst_mmu", 0x009, 2, {H, H, H}};*/
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("inst_mmu", 0x009, 2, {{H, H, H}});*/
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionAccessError>::vals
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("instruction_access_error", 0x00A, 400, {H, H, H});
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("instruction_access_error", 0x00A, 400, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<IllegalInstruction>::vals
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("illegal_instruction", 0x010, 620, {H, H, H});
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("illegal_instruction", 0x010, 620, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<PrivilegedOpcode>::vals
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("privileged_opcode", 0x011, 700, {P, SH, SH});
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("privileged_opcode", 0x011, 700, {{P, SH, SH}});
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<UnimplementedLDD>::vals
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{"unimp_ldd", 0x012, 6, {H, H, H}};*/
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("unimp_ldd", 0x012, 6, {{H, H, H}});*/
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<UnimplementedSTD>::vals
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{"unimp_std", 0x013, 6, {H, H, H}};*/
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("unimp_std", 0x013, 6, {{H, H, H}});*/
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template<> SparcFaultBase::FaultVals
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SparcFault<FpDisabled>::vals
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("fp_disabled", 0x020, 800, {P, P, H});
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("fp_disabled", 0x020, 800, {{P, P, H}});
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/* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
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* as a separate part. Therefore, we use the same code and TT */
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template<> SparcFaultBase::FaultVals
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SparcFault<VecDisabled>::vals =
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{"fp_disabled", 0x020, 800, {P, P, H}};
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SparcFault<VecDisabled>::vals
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("fp_disabled", 0x020, 800, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<FpExceptionIEEE754>::vals
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("fp_exception_ieee_754", 0x021, 1110, {P, P, H});
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("fp_exception_ieee_754", 0x021, 1110, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<FpExceptionOther>::vals
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("fp_exception_other", 0x022, 1110, {P, P, H});
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("fp_exception_other", 0x022, 1110, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<TagOverflow>::vals
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("tag_overflow", 0x023, 1400, {P, P, H});
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("tag_overflow", 0x023, 1400, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<CleanWindow>::vals
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("clean_window", 0x024, 1010, {P, P, H});
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("clean_window", 0x024, 1010, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<DivisionByZero>::vals
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("division_by_zero", 0x028, 1500, {P, P, H});
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("division_by_zero", 0x028, 1500, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<InternalProcessorError>::vals
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("internal_processor_error", 0x029, 4, {H, H, H});
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("internal_processor_error", 0x029, 4, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionInvalidTSBEntry>::vals
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("instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH});
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("instruction_invalid_tsb_entry", 0x02A, 210, {{H, H, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<DataInvalidTSBEntry>::vals
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("data_invalid_tsb_entry", 0x02B, 1203, {H, H, H});
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("data_invalid_tsb_entry", 0x02B, 1203, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<DataAccessException>::vals
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("data_access_exception", 0x030, 1201, {H, H, H});
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("data_access_exception", 0x030, 1201, {{H, H, H}});
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<DataAccessMMUMiss>::vals
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{"data_mmu", 0x031, 12, {H, H, H}};*/
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("data_mmu", 0x031, 12, {{H, H, H}});*/
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template<> SparcFaultBase::FaultVals
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SparcFault<DataAccessError>::vals
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("data_access_error", 0x032, 1210, {H, H, H});
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("data_access_error", 0x032, 1210, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<DataAccessProtection>::vals
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("data_access_protection", 0x033, 1207, {H, H, H});
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("data_access_protection", 0x033, 1207, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<MemAddressNotAligned>::vals
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("mem_address_not_aligned", 0x034, 1020, {H, H, H});
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("mem_address_not_aligned", 0x034, 1020, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<LDDFMemAddressNotAligned>::vals
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("LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H});
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("LDDF_mem_address_not_aligned", 0x035, 1010, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<STDFMemAddressNotAligned>::vals
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("STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H});
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("STDF_mem_address_not_aligned", 0x036, 1010, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<PrivilegedAction>::vals
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("privileged_action", 0x037, 1110, {H, H, SH});
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("privileged_action", 0x037, 1110, {{H, H, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<LDQFMemAddressNotAligned>::vals
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("LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H});
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("LDQF_mem_address_not_aligned", 0x038, 1010, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<STQFMemAddressNotAligned>::vals
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("STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H});
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("STQF_mem_address_not_aligned", 0x039, 1010, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionRealTranslationMiss>::vals
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("instruction_real_translation_miss", 0x03E, 208, {H, H, SH});
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("instruction_real_translation_miss", 0x03E, 208, {{H, H, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<DataRealTranslationMiss>::vals
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("data_real_translation_miss", 0x03F, 1203, {H, H, H});
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("data_real_translation_miss", 0x03F, 1203, {{H, H, H}});
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<AsyncDataError>::vals
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{"async_data", 0x040, 2, {H, H, H}};*/
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("async_data", 0x040, 2, {{H, H, H}});*/
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template<> SparcFaultBase::FaultVals
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SparcFault<InterruptLevelN>::vals
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("interrupt_level_n", 0x040, 0, {P, P, SH});
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("interrupt_level_n", 0x040, 0, {{P, P, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<HstickMatch>::vals
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("hstick_match", 0x05E, 1601, {H, H, H});
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("hstick_match", 0x05E, 1601, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<TrapLevelZero>::vals
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("trap_level_zero", 0x05F, 202, {H, H, SH});
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("trap_level_zero", 0x05F, 202, {{H, H, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<InterruptVector>::vals
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("interrupt_vector", 0x060, 2630, {H, H, H});
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("interrupt_vector", 0x060, 2630, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<PAWatchpoint>::vals
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("PA_watchpoint", 0x061, 1209, {H, H, H});
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("PA_watchpoint", 0x061, 1209, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<VAWatchpoint>::vals
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("VA_watchpoint", 0x062, 1120, {P, P, SH});
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("VA_watchpoint", 0x062, 1120, {{P, P, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<FastInstructionAccessMMUMiss>::vals
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("fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH});
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("fast_instruction_access_MMU_miss", 0x064, 208, {{H, H, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<FastDataAccessMMUMiss>::vals
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("fast_data_access_MMU_miss", 0x068, 1203, {H, H, H});
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("fast_data_access_MMU_miss", 0x068, 1203, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<FastDataAccessProtection>::vals
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("fast_data_access_protection", 0x06C, 1207, {H, H, H});
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("fast_data_access_protection", 0x06C, 1207, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionBreakpoint>::vals
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("instruction_break", 0x076, 610, {H, H, H});
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("instruction_break", 0x076, 610, {{H, H, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<CpuMondo>::vals
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("cpu_mondo", 0x07C, 1608, {P, P, SH});
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("cpu_mondo", 0x07C, 1608, {{P, P, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<DevMondo>::vals
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("dev_mondo", 0x07D, 1611, {P, P, SH});
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("dev_mondo", 0x07D, 1611, {{P, P, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<ResumableError>::vals
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("resume_error", 0x07E, 3330, {P, P, SH});
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("resume_error", 0x07E, 3330, {{P, P, SH}});
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template<> SparcFaultBase::FaultVals
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SparcFault<SpillNNormal>::vals
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("spill_n_normal", 0x080, 900, {P, P, H});
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("spill_n_normal", 0x080, 900, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<SpillNOther>::vals
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("spill_n_other", 0x0A0, 900, {P, P, H});
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("spill_n_other", 0x0A0, 900, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<FillNNormal>::vals
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("fill_n_normal", 0x0C0, 900, {P, P, H});
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("fill_n_normal", 0x0C0, 900, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<FillNOther>::vals
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("fill_n_other", 0x0E0, 900, {P, P, H});
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("fill_n_other", 0x0E0, 900, {{P, P, H}});
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template<> SparcFaultBase::FaultVals
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SparcFault<TrapInstruction>::vals
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("trap_instruction", 0x100, 1602, {P, P, H});
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("trap_instruction", 0x100, 1602, {{P, P, H}});
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/**
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* This causes the thread context to enter RED state. This causes the side
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