Changes to support PciDev as a new base class for devices which use PCI
--HG-- extra : convert_revision : fc2bc4399665344220b1a7e345ae6d2df03c9960
This commit is contained in:
Andrew Schultz
161
dev/pciconfigall.cc
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161
dev/pciconfigall.cc
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@@ -0,0 +1,161 @@
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/* $Id$ */
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/* @file
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* PCI Configspace implementation
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/scsi_ctrl.hh"
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#include "dev/pciconfigall.hh"
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#include "dev/pcidev.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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PCIConfigAll::PCIConfigAll(const string &name, Tsunami *t,
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Addr addr, Addr mask, MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu), tsunami(t)
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{
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//Put back pointer in tsunami
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tsunami->pciconfig = this;
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// Make all the pointers to devices null
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for(int x=0; x < MAX_PCI_DEV; x++)
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for(int y=0; y < MAX_PCI_FUNC; y++)
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devices[x][y] = NULL;
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}
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Fault
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PCIConfigAll::read(MemReqPtr &req, uint8_t *data)
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{
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DPRINTF(PCIConfigAll, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask);
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int reg = daddr & 0xFF;
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if (devices[device][func] == NULL) {
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switch (req->size) {
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// case sizeof(uint64_t):
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// *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
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// return No_Fault;
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case sizeof(uint32_t):
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*(uint32_t*)data = 0xFFFFFFFF;
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return No_Fault;
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case sizeof(uint16_t):
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*(uint16_t*)data = 0xFFFF;
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return No_Fault;
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case sizeof(uint8_t):
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*(uint8_t*)data = 0xFF;
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return No_Fault;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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} else {
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switch (req->size) {
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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devices[device][func]->ReadConfig(reg, req->size, data);
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return No_Fault;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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}
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DPRINTFN("Tsunami PCI Configspace ERROR: read daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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Fault
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PCIConfigAll::write(MemReqPtr &req, const uint8_t *data)
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{
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Addr daddr = (req->paddr & addr_mask);
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int reg = daddr & 0xFF;
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union {
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uint8_t byte_value;
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uint16_t half_value;
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uint32_t word_value;
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};
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if (devices[device][func] == NULL)
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panic("Attempting to write to config space on non-existant device\n");
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else {
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switch (req->size) {
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case sizeof(uint8_t):
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byte_value = *(uint8_t*)data;
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break;
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case sizeof(uint16_t):
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half_value = *(uint16_t*)data;
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break;
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case sizeof(uint32_t):
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word_value = *(uint32_t*)data;
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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}
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DPRINTF(PCIConfigAll, "write - va=%#x size=%d data=%#x\n",
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req->vaddr, req->size, word_value);
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devices[device][func]->WriteConfig(reg, req->size, word_value);
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return No_Fault;
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}
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void
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PCIConfigAll::serialize(std::ostream &os)
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{
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// code should be written
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}
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void
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PCIConfigAll::unserialize(Checkpoint *cp, const std::string §ion)
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{
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//code should be written
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(PCIConfigAll)
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SimObjectParam<Tsunami *> tsunami;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> mask;
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END_DECLARE_SIM_OBJECT_PARAMS(PCIConfigAll)
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BEGIN_INIT_SIM_OBJECT_PARAMS(PCIConfigAll)
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INIT_PARAM(tsunami, "Tsunami"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(mask, "Address Mask")
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END_INIT_SIM_OBJECT_PARAMS(PCIConfigAll)
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CREATE_SIM_OBJECT(PCIConfigAll)
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{
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return new PCIConfigAll(getInstanceName(), tsunami, addr, mask, mmu);
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}
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REGISTER_SIM_OBJECT("PCIConfigAll", PCIConfigAll)
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85
dev/pciconfigall.hh
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85
dev/pciconfigall.hh
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@@ -0,0 +1,85 @@
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution;
|
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* neither the name of the copyright holders nor the names of its
|
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* contributors may be used to endorse or promote products derived from
|
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* PCI Config space implementation.
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*/
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#ifndef __PCICONFIGALL_HH__
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#define __PCICONFIGALL_HH__
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#include "mem/functional_mem/mmap_device.hh"
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#include "dev/tsunami.hh"
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#include "dev/pcireg.h"
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#define MAX_PCI_DEV 32
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#define MAX_PCI_FUNC 8
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class PciDev;
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/**
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* PCI Config Space
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* All of PCI config space needs to return -1 on Tsunami, except
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* the devices that exist. This device maps the entire bus config
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* space and passes the requests on to TsunamiPCIDev devices as
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* appropriate.
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*/
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class PCIConfigAll : public MmapDevice
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{
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private:
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protected:
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/**
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* Pointer to the Tsunmi Object so we can communicate
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* to other Tsunami devices in need be.
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*/
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Tsunami *tsunami;
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public:
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/**
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* Pointers to all the devices that are registered with this
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* particular config space.
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*/
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PciDev* devices[MAX_PCI_DEV][MAX_PCI_FUNC];
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/**
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* The default constructor.
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*/
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PCIConfigAll(const std::string &name, Tsunami *t,
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Addr addr, Addr mask, MemoryController *mmu);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __PCICONFIGALL_HH__
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334
dev/pcidev.cc
Normal file
334
dev/pcidev.cc
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@@ -0,0 +1,334 @@
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
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* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
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* this software without specific prior written permission.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* A single PCI device configuration space entry.
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*/
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#include <list>
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#include <sstream>
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/misc.hh"
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#include "base/str.hh" // for to_number
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#include "base/trace.hh"
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#include "dev/pciareg.h"
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#include "dev/scsi_ctrl.hh"
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#include "dev/pcidev.hh"
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#include "dev/pciconfigall.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/param.hh"
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#include "sim/universe.hh"
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using namespace std;
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PciDev::PciDev(const string &name, PCIConfigAll *cf, uint32_t bus,
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uint32_t dev, uint32_t func)
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: MMapDevice(name), ConfigSpace(cf), Bus(bus), Device(dev), Function(func)
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{
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memset(config.data, 0, sizeof(config.data));
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// Setup pointer in config space to point to this entry
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if(cf->devices[dev][func] != NULL)
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panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
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else
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cf->devices[dev][func] = this;
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}
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void
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PciDev::ReadConfig(int offset, int size, uint8_t *data)
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{
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switch(size) {
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case sizeof(uint32_t):
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memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
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DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n",
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Device, Function, offset, *(uint32_t*)(config.data + offset));
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break;
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case sizeof(uint16_t):
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memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
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DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n",
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Device, Function, offset, *(uint16_t*)(config.data + offset));
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break;
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case sizeof(uint8_t):
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memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
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printf("data: %#x\n", *(uint8_t*)(config.data + offset));
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DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n",
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Device, Function, offset, *(uint8_t*)(config.data + offset));
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break;
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default:
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panic("Invalid Read Size");
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}
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}
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void
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PciDev::WriteConfig(int offset, int size, uint32_t data)
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{
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union {
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uint8_t byte_value;
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uint16_t half_value;
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uint32_t word_value;
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};
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word_value = data;
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DPRINTF(PCIDEV, "write device: %#x function: %#x register: %#x size: %#x data: %#x\n",
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Device, Function, offset, size, word_value);
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switch (size) {
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case sizeof(uint8_t): // 1-byte access
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switch (offset) {
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case PCI0_INTERRUPT_LINE:
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case PCI_CACHE_LINE_SIZE:
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*(uint8_t *)&config.data[offset] = byte_value;
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break;
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default:
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panic("writing to a read only register");
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}
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break;
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case sizeof(uint16_t): // 2-byte access
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switch (offset) {
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case PCI_COMMAND:
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case PCI_STATUS:
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case PCI_CACHE_LINE_SIZE:
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*(uint16_t *)&config.data[offset] = half_value;
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break;
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default:
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panic("writing to a read only register");
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}
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break;
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case sizeof(uint16_t)+1: // 3-byte access
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panic("invalid access size");
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case sizeof(uint32_t): // 4-byte access
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switch (offset) {
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case PCI0_BASE_ADDR0:
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case PCI0_BASE_ADDR1:
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case PCI0_BASE_ADDR2:
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case PCI0_BASE_ADDR3:
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case PCI0_BASE_ADDR4:
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case PCI0_BASE_ADDR5:
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// Writing 0xffffffff to a BAR tells the card to set the value of the bar
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// to size of memory it needs
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if (word_value == 0xffffffff) {
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// This is I/O Space, bottom two bits are read only
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if(config.data[offset] & 0x1) {
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*(uint32_t *)&config.data[offset] =
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~(BARSize[offset-PCI0_BASE_ADDR0] - 1) | (config.data[offset] & 0x3);
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} else {
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// This is memory space, bottom four bits are read only
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*(uint32_t *)&config.data[offset] =
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~(BARSize[(offset-PCI0_BASE_ADDR0)>>2] - 1) | (config.data[offset] & 0xF);
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}
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} else {
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// This is I/O Space, bottom two bits are read only
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if(config.data[offset] & 0x1) {
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*(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
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(config.data[offset] & 0x3);
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} else {
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// This is memory space, bottom four bits are read only
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*(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
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(config.data[offset] & 0xF);
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}
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}
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break;
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case PCI0_ROM_BASE_ADDR:
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if (word_value == 0xfffffffe)
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*(uint32_t *)&config.data[offset] = 0xffffffff;
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else
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*(uint32_t *)&config.data[offset] = word_value;
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break;
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case PCI_COMMAND:
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// This could also clear some of the error bits in the Status register
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// However they should never get set, so lets ignore it for now
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*(uint16_t *)&config.data[offset] = half_value;
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break;
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default:
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panic("writing to a read only register");
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}
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break;
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}
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}
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void
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PciDev::serialize(ostream &os)
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{
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SERIALIZE_ARRAY(config.data, 64);
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}
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void
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PciDev::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(config.data, 64);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciDev)
|
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|
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Param<int> VendorID;
|
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Param<int> DeviceID;
|
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Param<int> Command;
|
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Param<int> Status;
|
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Param<int> Revision;
|
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Param<int> ProgIF;
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Param<int> SubClassCode;
|
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Param<int> ClassCode;
|
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Param<int> CacheLineSize;
|
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Param<int> LatencyTimer;
|
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Param<int> HeaderType;
|
||||
Param<int> BIST;
|
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Param<uint32_t> BAR0;
|
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Param<uint32_t> BAR1;
|
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Param<uint32_t> BAR2;
|
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Param<uint32_t> BAR3;
|
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Param<uint32_t> BAR4;
|
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Param<uint32_t> BAR5;
|
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Param<uint32_t> CardbusCIS;
|
||||
Param<int> SubsystemVendorID;
|
||||
Param<int> SubsystemID;
|
||||
Param<uint32_t> ExpansionROM;
|
||||
Param<int> InterruptLine;
|
||||
Param<int> InterruptPin;
|
||||
Param<int> MinimumGrant;
|
||||
Param<int> MaximumLatency;
|
||||
Param<uint32_t> BAR0Size;
|
||||
Param<uint32_t> BAR1Size;
|
||||
Param<uint32_t> BAR2Size;
|
||||
Param<uint32_t> BAR3Size;
|
||||
Param<uint32_t> BAR4Size;
|
||||
Param<uint32_t> BAR5Size;
|
||||
|
||||
SimObjectParam<MemoryController *> mmu;
|
||||
SimObjectParam<PCIConfigAll*> cf;
|
||||
Param<Addr> addr;
|
||||
Param<Addr> mask;
|
||||
Param<uint32_t> bus;
|
||||
Param<uint32_t> device;
|
||||
Param<uint32_t> func;
|
||||
|
||||
|
||||
END_DECLARE_SIM_OBJECT_PARAMS(PciDev)
|
||||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(PciDev)
|
||||
|
||||
INIT_PARAM(VendorID, "Vendor ID"),
|
||||
INIT_PARAM(DeviceID, "Device ID"),
|
||||
INIT_PARAM_DFLT(Command, "Command Register", 0x00),
|
||||
INIT_PARAM_DFLT(Status, "Status Register", 0x00),
|
||||
INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
|
||||
INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
|
||||
INIT_PARAM(SubClassCode, "Sub-Class Code"),
|
||||
INIT_PARAM(ClassCode, "Class Code"),
|
||||
INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
|
||||
INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
|
||||
INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
|
||||
INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
|
||||
INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
|
||||
INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
|
||||
INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
|
||||
INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
|
||||
INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
|
||||
INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
|
||||
INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
|
||||
INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
|
||||
INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
|
||||
INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
|
||||
INIT_PARAM(InterruptLine, "Interrupt Line Register"),
|
||||
INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
|
||||
INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
|
||||
INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
|
||||
INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
|
||||
INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
|
||||
INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
|
||||
INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
|
||||
INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
|
||||
INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00),
|
||||
|
||||
INIT_PARAM(cf, "Pointer to Configspace device"),
|
||||
INIT_PARAM(bus, "PCI Bus Number"),
|
||||
INIT_PARAM(device, "PCI Device number"),
|
||||
INIT_PARAM(func, "PCI Function Number")
|
||||
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(PciDev)
|
||||
|
||||
CREATE_SIM_OBJECT(PciDev)
|
||||
{
|
||||
PciDev *dev = new PciDev(getInstanceName(), cf, bus, device, func);
|
||||
|
||||
dev->config.hdr.vendor = VendorID;
|
||||
dev->config.hdr.device = DeviceID;
|
||||
dev->config.hdr.command = Command;
|
||||
dev->config.hdr.status = Status;
|
||||
dev->config.hdr.revision = Revision;
|
||||
dev->config.hdr.progIF = ProgIF;
|
||||
dev->config.hdr.subClassCode = SubClassCode;
|
||||
dev->config.hdr.classCode = ClassCode;
|
||||
dev->config.hdr.cacheLineSize = CacheLineSize;
|
||||
dev->config.hdr.latencyTimer = LatencyTimer;
|
||||
dev->config.hdr.headerType = HeaderType;
|
||||
dev->config.hdr.bist = BIST;
|
||||
|
||||
dev->config.hdr.pci0.baseAddr0 = BAR0;
|
||||
dev->config.hdr.pci0.baseAddr1 = BAR1;
|
||||
dev->config.hdr.pci0.baseAddr2 = BAR2;
|
||||
dev->config.hdr.pci0.baseAddr3 = BAR3;
|
||||
dev->config.hdr.pci0.baseAddr4 = BAR4;
|
||||
dev->config.hdr.pci0.baseAddr5 = BAR5;
|
||||
dev->config.hdr.pci0.cardbusCIS = CardbusCIS;
|
||||
dev->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
|
||||
dev->config.hdr.pci0.subsystemID = SubsystemVendorID;
|
||||
dev->config.hdr.pci0.expansionROM = ExpansionROM;
|
||||
dev->config.hdr.pci0.interruptLine = InterruptLine;
|
||||
dev->config.hdr.pci0.interruptPin = InterruptPin;
|
||||
dev->config.hdr.pci0.minimumGrant = MinimumGrant;
|
||||
dev->config.hdr.pci0.maximumLatency = MaximumLatency;
|
||||
|
||||
dev->BARSize[0] = BAR0Size;
|
||||
dev->BARSize[1] = BAR1Size;
|
||||
dev->BARSize[2] = BAR2Size;
|
||||
dev->BARSize[3] = BAR3Size;
|
||||
dev->BARSize[4] = BAR4Size;
|
||||
dev->BARSize[5] = BAR5Size;
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
REGISTER_SIM_OBJECT("PciDev", PciDev)
|
||||
69
dev/pcidev.hh
Normal file
69
dev/pcidev.hh
Normal file
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2003 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* @file
|
||||
* PCI configspace devices
|
||||
*/
|
||||
|
||||
#ifndef __PCI_DEV_HH__
|
||||
#define __PCI_DEV_HH__
|
||||
|
||||
#include "mem/functional_mem/mmap_device.hh"
|
||||
#include "dev/pcireg.h"
|
||||
class PCIConfigAll;
|
||||
|
||||
/*
|
||||
* PCI device configuration device.
|
||||
* Each device is connected to a PCIConfigSpace device
|
||||
* which returns -1 for everything but the pcidevs that
|
||||
* register with it. This object registers with the PCIConfig space
|
||||
* object.
|
||||
*/
|
||||
class PciDev : public MMapDevice
|
||||
{
|
||||
private:
|
||||
uint32_t Bus;
|
||||
uint32_t Device;
|
||||
uint32_t Function;
|
||||
public:
|
||||
PciDev(const std::string &name, PCIConfigAll *cf, uint32_t bus,
|
||||
uint32_t dev, uint32_t func);
|
||||
|
||||
PCIConfigAll *ConfigSpace;
|
||||
PCIConfig config;
|
||||
uint32_t BARSize[6];
|
||||
|
||||
virtual void WriteConfig(int offset, int size, uint32_t data);
|
||||
virtual void ReadConfig(int offset, int size, uint8_t *data);
|
||||
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
};
|
||||
|
||||
#endif // __PCI_DEV_HH__
|
||||
Reference in New Issue
Block a user