derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

riscv: Get rid of ISA specific register types in Interrupts.

Browse Source 
Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/16122
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Austin Harris
2019-02-04 17:48:52 -06:00
committed by Austin Harris
parent 2775f55447
commit f0e2caf84f
1 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/arch/riscv/interrupts.hh
View File

@@ -125,10 +125,10 @@ class Interrupts : public SimObject
ip = 0;
}
MiscReg readIP() const { return (MiscReg)ip.to_ulong(); }
MiscReg readIE() const { return (MiscReg)ie.to_ulong(); }
void setIP(const MiscReg& val) { ip = val; }
void setIE(const MiscReg& val) { ie = val; }
uint64_t readIP() const { return (uint64_t)ip.to_ulong(); }
uint64_t readIE() const { return (uint64_t)ie.to_ulong(); }
void setIP(const uint64_t& val) { ip = val; }
void setIE(const uint64_t& val) { ie = val; }
void
serialize(CheckpointOut &cp)
@@ -150,4 +150,4 @@ class Interrupts : public SimObject
} // namespace RiscvISA
#endif // __ARCH_RISCV_INTERRUPT_HH__
#endif // __ARCH_RISCV_INTERRUPT_HH__