stdlib: cpu support for SimPoint and MAX_INSTS exit events

BaseCPU.py:
Linked "scheduleSimpointsInstStop" and "scheduleInstStopAnyThread" to
python

base.cc & base.hh:
Added scheduling functions for SimPoint and MAX_INSTS exit event.

abstract_core.py & base_cpu_core.py:
Added scheduling functions for SimPoint and MAX_INSTS exit event for stdlib
processor to access.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1259

Change-Id: I98a0f93b46a220fdb3f350d8da359c24b4d66a58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63153
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>

src/python/gem5/components/processors/abstract_core.py

@@ -25,7 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from abc import ABCMeta, abstractmethod
-from typing import Optional
+from typing import Optional, List
 
 from ...isas import ISA
 
@@ -120,3 +120,31 @@ class AbstractCore(SubSystem):
         This is used in the board to setup system-specific MMU settings.
         """
         raise NotImplementedError
+
+    @abstractmethod
+    def set_simpoint(self, inst_starts: List[int], init: bool) -> None:
+        """Schedule simpoint exit events for the core.
+
+        This is used to raise SIMPOINT_BEGIN exit events in the gem5 standard
+        library.
+
+        :param inst_starts: a list of SimPoints starting instructions
+        :param init: if it is True, the starting instructions will be scheduled
+        at the init stage of the core, else, the starting insructions will be
+        scheduled during the simulation
+        """
+        raise NotImplementedError("This core type does not support simpoints")
+
+    @abstractmethod
+    def set_inst_stop_any_thread(self, inst: int, init: bool) -> None:
+        """Schedule an exit event when any thread in this core reaches the
+        given number of instructions.
+
+        This is used to raise MAX_INSTS exit event in the gem5 standard library
+
+        :param inst: a number of instructions
+        :param init: if it is True, the exit event will be scheduled at the
+        init stage of the core, else, it will be scheduled during the
+        simulation
+        """
+        raise NotImplementedError("This core type does not support MAX_INSTS")

src/python/gem5/components/processors/base_cpu_core.py

@@ -24,7 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from typing import Optional
+from typing import Optional, List
 from ...utils.requires import requires
 from .abstract_core import AbstractCore
 
@@ -151,3 +151,17 @@ class BaseCPUCore(AbstractCore):
     @overrides(AbstractCore)
     def get_mmu(self) -> BaseMMU:
         return self.core.mmu
+
+    @overrides(AbstractCore)
+    def set_simpoint(self, inst_starts: List[int], init: bool) -> None:
+        if init:
+            self.core.simpoint_start_insts = inst_starts
+        else:
+            self.core.scheduleSimpointsInstStop(inst_starts)
+
+    @overrides(AbstractCore)
+    def set_inst_stop_any_thread(self, inst: int, init: bool) -> None:
+        if init:
+            self.core.max_insts_any_thread = inst
+        else:
+            self.core.scheduleInstStopAnyThread(inst)