stdlib: cpu support for SimPoint and MAX_INSTS exit events

BaseCPU.py:
Linked "scheduleSimpointsInstStop" and "scheduleInstStopAnyThread" to
python

base.cc & base.hh:
Added scheduling functions for SimPoint and MAX_INSTS exit event.

abstract_core.py & base_cpu_core.py:
Added scheduling functions for SimPoint and MAX_INSTS exit event for stdlib
processor to access.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1259

Change-Id: I98a0f93b46a220fdb3f350d8da359c24b4d66a58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63153
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>

src/cpu/BaseCPU.py

@@ -71,6 +71,8 @@ class BaseCPU(ClockedObject):
         PyBindMethod("totalInsts"),
         PyBindMethod("scheduleInstStop"),
         PyBindMethod("getCurrentInstCount"),
+        PyBindMethod("scheduleSimpointsInstStop"),
+        PyBindMethod("scheduleInstStopAnyThread"),
     ]
 
     @classmethod

src/cpu/base.cc

@@ -275,9 +275,7 @@ BaseCPU::init()
     // Set up instruction-count-based termination events, if any. This needs
     // to happen after threadContexts has been constructed.
     if (params().max_insts_any_thread != 0) {
-        const char *cause = "a thread reached the max instruction count";
-        for (ThreadID tid = 0; tid < numThreads; ++tid)
-            scheduleInstStop(tid, params().max_insts_any_thread, cause);
+        scheduleInstStopAnyThread(params().max_insts_any_thread);
     }
 
     // Set up instruction-count-based termination events for SimPoints
@@ -285,13 +283,11 @@ BaseCPU::init()
     // Simulation.py is responsible to take the necessary actions upon
     // exitting the simulation loop.
     if (!params().simpoint_start_insts.empty()) {
-        const char *cause = "simpoint starting point found";
-        for (size_t i = 0; i < params().simpoint_start_insts.size(); ++i)
-            scheduleInstStop(0, params().simpoint_start_insts[i], cause);
+        scheduleSimpointsInstStop(params().simpoint_start_insts);
     }
 
     if (params().max_insts_all_threads != 0) {
-        const char *cause = "all threads reached the max instruction count";
+        std::string cause = "all threads reached the max instruction count";
 
         // allocate & initialize shared downcounter: each event will
         // decrement this when triggered; simulation will terminate
@@ -661,7 +657,7 @@ BaseCPU::unserialize(CheckpointIn &cp)
 }
 
 void
-BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
+BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, std::string cause)
 {
     const Tick now(getCurrentInstCount(tid));
     Event *event(new LocalSimLoopExitEvent(cause, 0));
@@ -727,6 +723,23 @@ BaseCPU::traceFunctionsInternal(Addr pc)
     }
 }
 
+void
+BaseCPU::scheduleSimpointsInstStop(std::vector<Counter> inst_starts)
+{
+    std::string cause = "simpoint starting point found";
+    for (size_t i = 0; i < inst_starts.size(); ++i) {
+        scheduleInstStop(0, inst_starts[i], cause);
+    }
+}
+
+void
+BaseCPU::scheduleInstStopAnyThread(Counter max_insts)
+{
+    std::string cause = "a thread reached the max instruction count";
+    for (ThreadID tid = 0; tid < numThreads; ++tid) {
+        scheduleInstStop(tid, max_insts, cause);
+    }
+}
 
 BaseCPU::GlobalStats::GlobalStats(statistics::Group *parent)
     : statistics::Group(parent),

src/cpu/base.hh

@@ -436,7 +436,28 @@ class BaseCPU : public ClockedObject
      * @param insts Number of instructions into the future.
      * @param cause Cause to signal in the exit event.
      */
-    void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
+    void scheduleInstStop(ThreadID tid, Counter insts, std::string cause);
+
+    /**
+     * Schedule simpoint events using the scheduleInstStop function.
+     *
+     * This is used to raise a SIMPOINT_BEGIN exit event in the gem5 standard
+     * library.
+     *
+     * @param inst_starts A vector of number of instructions to start simpoints
+     */
+
+    void scheduleSimpointsInstStop(std::vector<Counter> inst_starts);
+
+    /**
+     * Schedule an exit event when any threads in the core reach the max_insts
+     * instructions using the scheduleInstStop function.
+     *
+     * This is used to raise a MAX_INSTS exit event in thegem5 standard library
+     *
+     * @param max_insts Number of instructions into the future.
+     */
+    void scheduleInstStopAnyThread(Counter max_insts);
 
     /**
      * Get the number of instructions executed by the specified thread

src/python/gem5/components/processors/abstract_core.py

@@ -25,7 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from abc import ABCMeta, abstractmethod
-from typing import Optional
+from typing import Optional, List
 
 from ...isas import ISA
 
@@ -120,3 +120,31 @@ class AbstractCore(SubSystem):
         This is used in the board to setup system-specific MMU settings.
         """
         raise NotImplementedError
+
+    @abstractmethod
+    def set_simpoint(self, inst_starts: List[int], init: bool) -> None:
+        """Schedule simpoint exit events for the core.
+
+        This is used to raise SIMPOINT_BEGIN exit events in the gem5 standard
+        library.
+
+        :param inst_starts: a list of SimPoints starting instructions
+        :param init: if it is True, the starting instructions will be scheduled
+        at the init stage of the core, else, the starting insructions will be
+        scheduled during the simulation
+        """
+        raise NotImplementedError("This core type does not support simpoints")
+
+    @abstractmethod
+    def set_inst_stop_any_thread(self, inst: int, init: bool) -> None:
+        """Schedule an exit event when any thread in this core reaches the
+        given number of instructions.
+
+        This is used to raise MAX_INSTS exit event in the gem5 standard library
+
+        :param inst: a number of instructions
+        :param init: if it is True, the exit event will be scheduled at the
+        init stage of the core, else, it will be scheduled during the
+        simulation
+        """
+        raise NotImplementedError("This core type does not support MAX_INSTS")

src/python/gem5/components/processors/base_cpu_core.py

@@ -24,7 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from typing import Optional
+from typing import Optional, List
 from ...utils.requires import requires
 from .abstract_core import AbstractCore
 
@@ -151,3 +151,17 @@ class BaseCPUCore(AbstractCore):
     @overrides(AbstractCore)
     def get_mmu(self) -> BaseMMU:
         return self.core.mmu
+
+    @overrides(AbstractCore)
+    def set_simpoint(self, inst_starts: List[int], init: bool) -> None:
+        if init:
+            self.core.simpoint_start_insts = inst_starts
+        else:
+            self.core.scheduleSimpointsInstStop(inst_starts)
+
+    @overrides(AbstractCore)
+    def set_inst_stop_any_thread(self, inst: int, init: bool) -> None:
+        if init:
+            self.core.max_insts_any_thread = inst
+        else:
+            self.core.scheduleInstStopAnyThread(inst)